Timing analysis of network on chip architectures for MP-SoC platforms

Microelectronics Journal

Volumn 36, Issue 9, 2005, Pages 833-845

  Grecu, Cristian ^a   Pande, Partha Pratim ^a   Ivanov, André ^a   Saleh, Res ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Bus; MP SoC; NoC; Pipelining; Scalability

Indexed keywords

EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTELLECTUAL PROPERTY; MULTIPROCESSING SYSTEMS; REAL TIME SYSTEMS; SIGNAL PROCESSING; TELECOMMUNICATION NETWORKS;

BUS; MP-SOC; NOC; SCALABILITY;

MICROPROCESSOR CHIPS;

EID: 23844498131     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2005.03.006     Document Type: Conference Paper

References (28)

1. L. Benini, and G. De Micheli Networks on Chips: a New SoC paradigm computer 35 1 2002 70 78
2. P. Magarshack, and P.G. Paulin System-on-Chip beyond the nanometer wall Proceedings of DAC, Anaheim, USA, June 2-6 2003 pp. 419-424
3. M. Horowitz, and B. Dally How scaling will change processor architecture Proceedings of ISSCC, San Francisco, USA, February 15-19 2004 pp. 132-133
4. M. Horowitz The future of wires Proceedings of the IEEE 89 4 2001 490 504
5. K.C. Saraswat Technology and reliability constrained future copper interconnects - part II: performance implications IEEE Transactions on Electron Devices 49 4 2002 598 604
6. Cheng-Ta Hsieh, and Massoud Pedram Architectural energy optimization by bus splitting IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21 4 2002 408 414
7. Y. Zorian Guest editor's introduction: what is infrastructure IP? IEEE Design & Test of Computers 19 3 2002 3 5
8. ITRS 2003 Documents http://public.itrs.net/Files/2003ITRS/Home2003.htm.
9. AMBA Bus specification, http://www.arm.com.
10. Wishbone Service Center, http://www.silicore.net/wishbone.htm.
11. CoreConnect Specification, http://www-3.ibm.com/chips/products/ coreconnect/.
12. D. Wingard MicroNetwork-based integration for SoCs Proceedings of DAC, Las Vegas, Nevada, USA, June 18-22 2001 pp. 673-677
13. Open Core Protocol, www.ocpip.org.
14. MIPS SoC-it, www.mips.com.
15. S. Kumar A network on chip architecture and design methodology Proceedings of ISVLSI 2002 pp. 117-124
16. W.J. Dally, and B. Towles Route packets, not wires: on-chip interconnection networks Proceedings of DAC, Las Vegas, Nevada, USA, June 18-22 2001 pp. 683-689
17. I. Saastamoinen Interconnect IP node for future system-on-chip designs Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications 2002 pp. 116-120
18. P. Guerrier, and A. Greiner A generic architecture for on-chip packet-switched interconnections Proceedings of DATE, Paris, France, March 27-30 2000 pp. 250-256
19. P.P. Pande, C. Grecu, A. Ivanov, and R. Saleh Design of a switch for network on chip applications Proceedings of ISCAS, Bangkok, May vol. 5 2003 pp. 217-220
20. C. Grecu, P.P. Pande, A. Ivanov, and R. Saleh Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs Great Lakes Symposium on VLSI, Boston, USA, April 26-28 2004 pp. 192-195
21. D. Sylvester, and K. Keutzer Impact of small process geometries on microarchitectures in systems on a chip Proceedings of the IEEE 89 4 2001 467 489
22. D.A. Hodges, H.G. Jackson, and R. Saleh Analysis and Design of Digital Integrated Circuits third ed. 2003 McGraw-Hill New York
23. J. Duato, S. Yalamanchili, and L. Ni Interconnection Networks - An Engineering Approach 2002 Morgan Kaufmann
24. Hang-Sheng Wang, L.S. Peh, and S. Malik A power model for routers: modeling alpha 21364 and infiniband routers Proceedings of 10th Symposium on High Performance Interconnects, Stanford, California, USA 2002 pp. 21-27
25. P.P. Pande, C. Grecu, A. Ivanov, and R. Saleh High-throughput switch-based interconnect for future SoCs Proceedings of third IEEE International Workshop on System-on-Chip for Real-Time Applications, June 30-July 2, Calgary, Canada 2003 pp. 304-310
26. W.J. Dally, C.L. Seitz (1986) The Torus Routing Chip, Technical Report 5208: TR: 86; Computer Science Department, California Institute of Technology, 1986, pp. 1-19.
27. W.J. Dally Virtual channel flow control IEEE Transactions on Parallel and Distributed Systems 3 2 1992 194 205
28. K.S. Stevens Energy and performance models for clocked and asynchronous communication Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems, Vancouver, Canada, May 2003 pp. 56-66