Carbon nanotube field-effect transistors for high-performance digital circuits - DC analysis and modeling toward optimum transistor structure

IEEE Transactions on Electron Devices

Volumn 53, Issue 11, 2006, Pages 2711-2717

  Raychowdhury, Arijit ^a   Keshavarzi, Ali ^b   Kurtin, Juanita ^b   De, Vivek ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Carbon nanotube field effect transistors (CNFETs); Dc analysis; High performance circuits; Modeling; Noise margin; Voltage swing

Indexed keywords

CARBON NANOTUBES; CARRIER MOBILITY; DIGITAL CIRCUITS; MOS DEVICES; MOSFET DEVICES; POWER INTEGRATED CIRCUITS; SCHOTTKY BARRIER DIODES; SEMICONDUCTOR DEVICE MODELS;

CARBON NANOTUBE FIELD EFFECT TRANSISTORS; DC ANALYSIS; HIGH-PERFORMANCE DIGITAL CIRCUITS; NOISE MARGIN; VOLTAGE SWING;

FIELD EFFECT TRANSISTORS;

EID: 33750597000     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.883816     Document Type: Article

References (35)

1. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimandi, "Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
2. S. Borkar, "Technology trends and design challenges for microprocessor design," in Proc. 24th ESSCIRC, Sep. 22-24, 1998, pp. 7-8.
3. A. Keshavarzi, J. W. Tschanz, S. Narendra, V. De, W. R. Daasch, K. Roy, M. Sachdev, and C. F. Hawkins, "Leakage and process variation effects in current testing on future CMOS circuits," IEEE Des. Test Comput., vol. 19, no. 5, pp. 36-43, Sep./Oct. 2002.
4. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
5. B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, "Tri-Gate fully-depleted CMOS transistors: Fabrication, design and layout," in VLSI Symp. Tech. Dig., Jun. 2003, pp. 133-134.
6. S. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. McIntyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.
7. S. Datta, T. Ashley, R. Chau, K. Hilton, R. Jefferies, T. Martin, and T. Phillips, "85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications," in IEDM Tech. Dig., Dec. 2005, pp. 783-786.
8. P. L. McEuen, M. S. Fuhrer, and H. Park, "Single-walled carbon nanotube electronics," IEEE Trans. Nanotechnol., vol. 1, no. 1, pp. 78-85, Mar. 2002.
9. P. Avouris, "Supertubes [carbon nanotubes]," IEEE Spectrum, vol. 41, no. 8, pp. 40-45, Aug. 2004.
10. P. Avouris, J. Appenzeller, V. Derycke, R. Martel, and S. Wind, "Carbon nanotube electronics," in IEDM Tech. Dig., Dec. 2002, pp. 281-284.
11. V. Derycke, R. Martel, J. Appenzeller, and P. Avouris, "Carbon nanotube inter- and intramolecular logic gates," Nano Letters, vol. 1, no. 9, pp. 453-456, 2001.
12. A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, "Logic circuits with carbon nanotube transistors," Science, vol. 294, no. 5545, pp. 1317-1320, Nov. 2001.
13. M. Freitag, M. Radosavljevic, Y. Zhou, A. T. Johnson, and W. F. Smith, "Controlled creation of a carbon nanotube diode by a scanned gate," Appl. Phys. Lett., vol. 79, no. 20, pp. 3326-3328, Nov. 2001.
14. A. Javey, J. Guo, Q. Wang, M. Lundstrom, and H. Dai, "Ballistic carbon nanotube field-effect transistors," Nature, vol. 4, no. 24, pp. 654-657, 2003.
15. J. Appenzeller, J. Knoch, M. Radosavljevic, and P. Avouris, "Multimode transport in schottky-barrier carbon-nanotube field-effect transistors," Phys. Rev. Lett., vol. 92, no. 22, p. 226802, Jun. 2004.
16. M. Radosavljevic, S. Heinze, J. Tersoff, and P. Avouris, "Drain voltage scaling in carbon nanotube transistors," Appl. Phys. Lett., vol. 83, no. 12, p. 2435, Sep. 2003.
17. A. Javey, J. Guo, D. Farmer, Q. Wang, E. Yenilmez, R. Gordon, M. Lundstrom, and H. Dai, "Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays," Nano Lett., vol. 4, no. 7, pp. 1319-1322, Jun. 2004.
18. J. Chen, C. Clinke, A. Afzali, and P. Avouris, "Air-stable chemical doping of carbon nanotube transistors," in Proc. Device Res. Conf., 2004, pp. 137-138.
19. A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon, and H. Dai, "High performance n-type carbon nanotube field-effect transistors with chemically doped contacts," Nano Lett., vol. 5, no. 2, pp. 345-348, Feb. 2005.
20. Y.-M. Lin, J. Appenzeller, J. Knoch, and P. Avouris, "High-performance carbon nanotube field-effect transistor with tunable polarities," IEEE Trans. Nanotechnol., vol. 4, no. 5, pp. 481-489, Sep. 2005.
21. J. Guo, A. Javey, H. Dai, S. Datta, and M. Lundstrom, "Predicted Performance Advantages of Carbon Nanotube Transistors With Doped Nanotubes as Source/Drain," cond-mat/0309039. [Online]. Available: http://arxiv.org/abs/cond-mat/0309039
22. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, "Band-to-band tunneling in carbon nanotube field-effect transistors," Phys. Rev. Lett., vol. 93, no. 19, p. 196805, Nov. 2004.
23. S. O. Koswatta, D. E. Nikonov, and M. S. Lundstrom, "Computational study of carbon nanotube p-i-n tunnel FETs," in IEDM Tech. Dig., Dec. 2005, pp. 525-528.
24. J. Guo, S. Datta, M. Lundstrom, and M. P. Anantram, "Multi-scale modeling of carbon nanotube transistors," Int. J. Multiscale Comput. Eng., vol. 2, p. 257, 2004.
25. J. Guo, A. Javey, H. Dai, and M. Lundstrom, "Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistors," in IEDM Tech. Dig., Dec. 2004, pp. 703-706.
26. S. Datta, Electronic Transport inMesoscopic Systems. Cambridge, U.K.: Cambridge Univ. Press, 1995.
27. R. Venugopal, Z. Ren, S. Datta, M. Lundstrom, and D. Jovanovic, "Simulating quantum transport in nanoscale MOSFETs: Real vs. mode space approaches," J. Appl. Phys., vol. 92, no. 7, pp. 3730-3739, Oct. 2002.
28. S. Datta, "Nanoscale device modeling: The green's function method," Superlattices Microstruct., vol. 28, no. 4, pp. 253-278, Oct. 2000.
29. J. Tersoff, "Schottky barrier heights and the continuum of gap states," Phys. Rev. Lett., vol. 52, no. 6, pp. 465-568, Feb. 1984.
30. M. Freitag, J. Chen, Tersoff, J. C. Tsang, Q. Fu, J. Liu, and P. Avouris, "Mobile ambipolar domain in carbon-nanotube infrared emitters," Phys. Rev. Lett., vol. 93, no. 7, p. 076803, Aug. 2004.
31. J. Guo and M. Lundstrom, "On the role of phonon scattering in carbon nanotube transistors," Appl. Phys. Lett., vol. 86, no. 19, p. 193103, May 2005.
32. R. Martel, V. Derycke, C. Lavoie, J. Appenzeller, K. K. Chan, J. Tersoff, and P. Avouris, "Ambipolar electrical transport in semiconducting singlewall carbon nanotubes," Phys. Rev. Lett., vol. 87, no. 25, p. 256805, Dec. 2001.
33. A. Raychowdhury, J. Guo, K. Roy, and M. Lundstrom, "Choice of flatband voltage, VDD and diameter of ambipolar schottky-barrier carbon nanotube transistors in digital circuit design," presented at the 4th IEEE Nano Conf., Munich, Germany, Aug. 2004, TH-2-2-1.
34. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley, 1993.
35. A. Keshavarzi, A. Raychowdhury, J. Kurtin, K. Roy, and V. De, "Carbon nanotube field-effect transistors for high-performance digital circuits_Transient analysis, parasitics, and scalability," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2718-2726, 2006.