-
1
-
-
26244453976
-
"Multi-scale modeling of carbon nanotube transistors"
-
J. Guo, S. Datta, M. Lundstrom, and M. P. Anantram, "Multi-scale modeling of carbon nanotube transistors," Int. J. Multiscale Comput. Eng., vol. 2, no. 2, p. 257, 2004.
-
(2004)
Int. J. Multiscale Comput. Eng.
, vol.2
, Issue.2
, pp. 257
-
-
Guo, J.1
Datta, S.2
Lundstrom, M.3
Anantram, M.P.4
-
2
-
-
4143096759
-
"Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays"
-
A. Javey, J. Guo, D. Farmer, Q. Wang, E. Yenilmez, R. Gordon, M. Lundstrom, and H. Dai, "Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays," Nano Lett., vol. 4, no. 7, pp. 1319-1322, 2004.
-
(2004)
Nano Lett.
, vol.4
, Issue.7
, pp. 1319-1322
-
-
Javey, A.1
Guo, J.2
Farmer, D.3
Wang, Q.4
Yenilmez, E.5
Gordon, R.6
Lundstrom, M.7
Dai, H.8
-
3
-
-
0026255002
-
"FASTCAP: A multipole-accelerated 3-D capacitance extraction program"
-
Nov
-
K. Nabors and J. K. White, "FASTCAP: A multipole-accelerated 3-D capacitance extraction program," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 10, no. 11, pp. 1447-1459, Nov. 1991.
-
(1991)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.10
, Issue.11
, pp. 1447-1459
-
-
Nabors, K.1
White, J.K.2
-
5
-
-
84966681553
-
"Studies on size effects of copper interconnect lines"
-
in Oct
-
W. Wu and K. Maex, "Studies on size effects of copper interconnect lines," in Proc. Solid-State and Integr.-Circuit Technol., Oct. 2001, vol. 1, pp. 416-418.
-
(2001)
Proc. Solid-State and Integr.-Circuit Technol.
, vol.1
, pp. 416-418
-
-
Wu, W.1
Maex, K.2
-
6
-
-
33750603146
-
"Gate capacitance optimization for arrays of carbon nanotube field-effect transistors"
-
in Jun
-
W. Xinlin, H.-S. P. Wong, P. Oldiges, and R. J. Miller, "Gate capacitance optimization for arrays of carbon nanotube field-effect transistors," in Proc. Device Res. Conf., Jun. 2003, pp. 87-88.
-
(2003)
Proc. Device Res. Conf.
, pp. 87-88
-
-
Xinlin, W.1
Wong, H.-S.P.2
Oldiges, P.3
Miller, R.J.4
-
7
-
-
33847693112
-
"Performance assessment of subpercolating nanobundle network transistors by an analytical model"
-
in Dec
-
N. Pimparkar, J. Guo, and M. Alam, "Performance assessment of subpercolating nanobundle network transistors by an analytical model," in IEDM Tech. Dig., Dec. 2005, pp. 534-537.
-
(2005)
IEDM Tech. Dig.
, pp. 534-537
-
-
Pimparkar, N.1
Guo, J.2
Alam, M.3
-
8
-
-
79956043573
-
"Metal-insulator-semiconductor electrostatics of carbon nanotubes"
-
Aug
-
J. Guo, S. Goasguen, M. Lundstrom, and S. Datta, "Metal-insulator-semiconductor electrostatics of carbon nanotubes," Appl. Phys. Lett., vol. 81, no. 8, pp. 1486-1490, Aug. 2002.
-
(2002)
Appl. Phys. Lett.
, vol.81
, Issue.8
, pp. 1486-1490
-
-
Guo, J.1
Goasguen, S.2
Lundstrom, M.3
Datta, S.4
-
9
-
-
0035475617
-
"Sub-60-nm quasi-planar FinFETs fabricated using a simplified process"
-
Oct
-
N. Lindert, L. Chang, C. Yang-Kyu, E. H. Anderson, L. Wen-Chin, K. Tsu-Jae, J. Bokor, and C. Hu, "Sub-60-nm quasi-planar FinFETs fabricated using a simplified process," IEEE Electron Device Lett., vol. 22, no. 10, pp. 487-489, Oct. 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, Issue.10
, pp. 487-489
-
-
Lindert, N.1
Chang, L.2
Yang-Kyu, C.3
Anderson, E.H.4
Wen-Chin, L.5
Tsu-Jae, K.6
Bokor, J.7
Hu, C.8
-
10
-
-
84907703268
-
"Layout density analysis of FinFETs"
-
in
-
K. G. Anil, K. Henson, S. Biesemans, and N. Collaert, "Layout density analysis of FinFETs," in Proc. Eur. Solid-State Device Res., 2003, pp. 139-142.
-
(2003)
Proc. Eur. Solid-State Device Res.
, pp. 139-142
-
-
Anil, K.G.1
Henson, K.2
Biesemans, S.3
Collaert, N.4
-
11
-
-
15844407150
-
"Benchmarking nanotechnology for high-performance and low-power logic transistor applications"
-
Mar
-
R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking nanotechnology for high-performance and low-power logic transistor applications," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 153-158, Mar. 2005.
-
(2005)
IEEE Trans. Nanotechnol.
, vol.4
, Issue.2
, pp. 153-158
-
-
Chau, R.1
Datta, S.2
Doczy, M.3
Doyle, B.4
Jin, B.5
Kavalieros, J.6
Majumdar, A.7
Metz, M.8
Radosavljevic, M.9
-
12
-
-
33750585580
-
"85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications"
-
in Dec
-
S. Datta, T. Ashley, R. Chau, K. Hilton, R. Jefferies, T. Martin, and T. Phillips, "85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications," in IEDM Tech. Dig., Dec. 2005, pp. 783-786.
-
(2005)
IEDM Tech. Dig.
, pp. 783-786
-
-
Datta, S.1
Ashley, T.2
Chau, R.3
Hilton, K.4
Jefferies, R.5
Martin, T.6
Phillips, T.7
-
13
-
-
33750597000
-
"Carbon nanotube field-effect transistors for high-performance digital circuits - DC analysis and modeling toward optimum transistor structure"
-
A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, "Carbon nanotube field-effect transistors for high-performance digital circuits - DC analysis and modeling toward optimum transistor structure," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2711-2717, 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.11
, pp. 2711-2717
-
-
Raychowdhury, A.1
Keshavarzi, A.2
Kurtin, J.3
De, V.4
Roy, K.5
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