A timing-aware probabilistic model for single-event-upset analysis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 10, 2006, Pages 1130-1139

  Rejimon, Thara ^a   Bhanja, Sanjukta ^a  

^a University of South Florida   (United States)

Author keywords

Bayesian inference; Probabilistic modeling; Radiation tolerant designs; SEUs sensitivity; Single event upset (SEU)

Indexed keywords

COSMIC RAYS; GATES (TRANSISTOR); PROBABILISTIC LOGICS; PROBABILITY DISTRIBUTIONS; RANDOM PROCESSES; SENSITIVITY ANALYSIS;

BAYESIAN INFERENCE; BENCHMARK CIRCUITS; RADIATION TOLERANT DESIGNS; SINGLE EVENT UPSET (SEU) SENSITIVITY;

LOGIC CIRCUITS;

EID: 33750588360     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.884165     Document Type: Article

References (19)

1. K. Mohanram and N. A. Touba, "Cost-effective approach for reducing soft error failure rate in logic circuits," in Proc. Int. Test Conf., 2003, pp. 893-901.
2. S. Bhanja and N. Ranganathan, "Switching activity estimation of VLSI circuits using bayesian networks," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 2, pp. 558-567, Feb. 2003.
3. P. Shivakumar, "Modeling the effect of technology trends on the soft error rate of combinational logic," in Proc. Int. Conf. Dependable Syst. Netw., 2002, pp. 389-398.
4. M. Violante, "Accurate single-event-transient analysis via zero-delay logic simulation," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 2113-2118, Dec. 2003.
5. T. Rejimon and S. Bhanja, "An accurate probabilistic model for error detection," in Proc. IEEE Int. Conf. VLSI Des., 2005, pp. 717-722.
6. T. Karnik and P. Hazucha, "Characterization of soft errors caused by single event upsets in CMOS processes," IEEE Trans. Dependable Secure Comput., vol. 1-2, pp. 128-143, Apr.-June 2004.
7. V. Degalahal, R. Rajaram, N. Vijaykrishan, Y. Xie, and M. J. Irwin, "The effect of threshold voltages on soft error rate," in Proc. 5th Int. Symp. Quality Electron. Des., 2004, pp. 503-508.
8. Y. S. Dhillon, A. U. Diril, and A. Chatterjee, "Softor tolerance analysis and optimization of nanometer circuits," in Proc. Des., Autom. Test Eur., 2005, pp. 288-293.
9. S. Krishnaswamy, G. S. Viamontes, I. L. Markov, and J. P. Hayes, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices," in Proc. Des. Autom. Test Eur. (DATE), 2005, pp. 282-287.
10. P. K. Samudrala, J. Ramos, and S. Katkoori, "Selective triple modular redundancy (STMR) based single-event-upset (SEU) tolerant synthesis for FPGAS," IEEE Trans. Nucl. Sci., vol. 51, no. 5, pp. 2957-2969, Oct. 2004.
11. C. Zhao, X. Bai, and S. Dey, "A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits," in Proc. Des. Autom. Conf., 2004, pp. 894-899.
12. M. Zhang and N. R. Shanbhag, "A soft error rate analysis (SERA) methodology," in Proc. Int. Conf. Comput.-Aided Des., 2004, pp. 111-118.
13. S. Manich and J. Figueras, "Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model," in Proc. Eur. Des. Test Conf., 1997, pp. 597-602.
14. S. Bhanja, K. Lingasubramanian, and N. Ranganathan, "A stimulus-free probabilistic switching model for sequential circuits," ACM Trans. Des. Autom. Election. Syst., vol. 11-3, pp. 773-796, 2006.
15. M. Henrion, "Propagation of uncertainty by probabilistic logic sampling in Bayes' networks," in Uncertainty in Artificial Intelligence. New York: Elsevier Science, 1988.
16. J. Pearl, Probabilistic Reasoning in Intelligent Systems: Network of Plausible Inference. San Mateo, CA: Morgan Kaufmann, 1988.
17. R. G. Cowell, A. P. David, S. L. Lauritzen, and D. J. Spiegelhalter, Probabilistic Networks and Expert Systems. New York: Springer-Verlag, 1999.
18. I. Sutherland, R. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. San Mateo, CA: Morgan Kaufmann, 1999.
19. N. Ramalingam and S. Bhanja, "Causal probabilistic input dependency learning for switching model in VLSI circuits," in Proc. ACM GLSVLSI, 2005, pp. 112-115.