Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

Proceedings of European Design and Test Conference

Volumn , Issue , 1997, Pages 597-602

  Manich, S ^a   Figueras, J ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL SWITCHING; COMPUTER SIMULATION; EQUIVALENT CIRCUITS;

AUTOMATIC TEST AND PATTERN GENERATION TOOLS; VARIABLE DELAY MODEL;

COMBINATORIAL CIRCUITS;

EID: 0030646135     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)