-
2
-
-
0141638630
-
Switching activity estimation of VLSI circuits using Bayesian networks
-
BHANJA, S. AND RANGANATHAN, N. 2003. Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. VLSI Syst. 11, 4 (Aug.), 558-567.
-
(2003)
IEEE Trans. VLSI Syst.
, vol.11
, Issue.4 AUG
, pp. 558-567
-
-
Bhanja, S.1
Ranganathan, N.2
-
3
-
-
12344287124
-
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
-
BHANJA, S. AND RANGANATHAN, N. 2004. Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. VLSI Syst. 12, 12 (Dec.), 1387-1397.
-
(2004)
IEEE Trans. VLSI Syst.
, vol.12
, Issue.12 DEC
, pp. 1387-1397
-
-
Bhanja, S.1
Ranganathan, N.2
-
4
-
-
0026913667
-
Symbolic Boolean manipulation with ordered binary-decision diagrams
-
BRYANT, R. E. 1992. Symbolic Boolean manipulation with ordered binary-decision diagrams. ACM Comput. Surv. 24, 3 (Sept.), 293-318.
-
(1992)
ACM Comput. Surv.
, vol.24
, Issue.3 SEPT
, pp. 293-318
-
-
Bryant, R.E.1
-
5
-
-
0030720153
-
An efficient statistical method to estimate average power in sequential circuits considering input sensitivities
-
CHEN, Z. AND ROY, K. 1997. An efficient statistical method to estimate average power in sequential circuits considering input sensitivities. In Proceedings of the ASIC Conference and Exhibit, 189-193.
-
(1997)
Proceedings of the ASIC Conference and Exhibit
, pp. 189-193
-
-
Chen, Z.1
Roy, K.2
-
6
-
-
0003687180
-
-
Springer Verlag, New York
-
COWELL, R. G., DAVID, A. P., LAURITZEN, S. L., AND SPIEGELHALTER, D. J. 1999. Probabilistic Networks and Expert Systems. Springer Verlag, New York.
-
(1999)
Probabilistic Networks and Expert Systems
-
-
Cowell, R.G.1
David, A.P.2
Lauritzen, S.L.3
Spiegelhalter, D.J.4
-
7
-
-
0032206035
-
Gate-level power estimation using tagged probabilistic simulation
-
DING, C. S., TSUI, C. Y., AND PEDRAM, M. 1998. Gate-Level power estimation using tagged probabilistic simulation. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 17, 11 (Nov.), 1099-1107.
-
(1998)
IEEE Trans. Comput. Aided Des. Integrated Circuits Syst.
, vol.17
, Issue.11 NOV
, pp. 1099-1107
-
-
Ding, C.S.1
Tsui, C.Y.2
Pedram, M.3
-
8
-
-
0026882401
-
Testability measures in pseudorandom testing
-
ERCOLANI, S., FAVALLI, M., DAMIANI, M., OLIVO, P., AND RICCO, B. 1992. Testability measures in pseudorandom testing. IEEE Trans. CAD 11, 794-800.
-
(1992)
IEEE Trans. CAD
, vol.11
, pp. 794-800
-
-
Ercolani, S.1
Favalli, M.2
Damiani, M.3
Olivo, P.4
Ricco, B.5
-
10
-
-
0028599185
-
Probabilistic analysis of large finite state machines
-
HACHTEL, G. D., MACII, E., PARDO, A., AND SOMENZI, F. 1994. Probabilistic analysis of large finite state machines. In Proceedings of the Design Automation Conference, 270-275.
-
(1994)
Proceedings of the Design Automation Conference
, pp. 270-275
-
-
Hachtel, G.D.1
Macii, E.2
Pardo, A.3
Somenzi, F.4
-
11
-
-
85012775611
-
Propagation of uncertainty in Bayes' networks by probabilistic logic sampling
-
Elsevier Science, New York
-
HENRION, M. 1988. Propagation of uncertainty in Bayes' networks by probabilistic logic sampling. In Uncertainty in Artificial Intelligence. Elsevier Science, New York, 149-163.
-
(1988)
Uncertainty in Artificial Intelligence
, pp. 149-163
-
-
Henrion, M.1
-
12
-
-
84859275427
-
-
HUGIN. 2006. Hugin. url: http://www.hugin.com/.
-
(2006)
Hugin
-
-
-
13
-
-
0005059765
-
Dhugin: A computational system for dynamic time-sliced Bayesian networks
-
KJAERULFF, U. 1995. Dhugin: A computational system for dynamic time-sliced Bayesian networks. Int. J. Forecasting 11, 89-111.
-
(1995)
Int. J. Forecasting
, vol.11
, pp. 89-111
-
-
Kjaerulff, U.1
-
14
-
-
0035301557
-
Power estimation for large sequential circuits
-
KOZHAYA, J. N. AND NAJM, F. N. 2001. Power estimation for large sequential circuits. IEEE Trans. VLSI Syst. 9, 2, 400-406.
-
(2001)
IEEE Trans. VLSI Syst.
, vol.9
, Issue.2
, pp. 400-406
-
-
Kozhaya, J.N.1
Najm, F.N.2
-
15
-
-
0030646135
-
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model
-
MANICH, S. AND FIGUERAS, J. 1997. Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. In Proceedings of the European Design and Test Conference, 597-602.
-
(1997)
Proceedings of the European Design and Test Conference
, pp. 597-602
-
-
Manich, S.1
Figueras, J.2
-
16
-
-
0033692171
-
Theoretical bounds for switching activity analysis in finite-state machines
-
MARCULESCU, D., MARCULESCU, R., AND PEDRAM, M. 2000. Theoretical bounds for switching activity analysis in finite-state machines. IEEE Trans. VLSI Syst. 8, 3, 335-339.
-
(2000)
IEEE Trans. VLSI Syst.
, vol.8
, Issue.3
, pp. 335-339
-
-
Marculescu, D.1
Marculescu, R.2
Pedram, M.3
-
17
-
-
0032003360
-
Probabilistic modeling of dependencies during switching activity analysis
-
MARCULESCU, R., MARCULESCU, D., AND PEDRAM, M. 1998. Probabilistic modeling of dependencies during switching activity analysis. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 17, 2 (Feb.), 73-83.
-
(1998)
IEEE Trans. Comput. Aided Des. Integrated Circuits Syst.
, vol.17
, Issue.2 FEB
, pp. 73-83
-
-
Marculescu, R.1
Marculescu, D.2
Pedram, M.3
-
18
-
-
0032661169
-
Sequence compaction for power estimation: Theory and practice
-
MARCULESCU, R., MARCULESCU, D., AND PEDRAM, M. 1999. Sequence compaction for power estimation: Theory and practice. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 18, 7, 973-993.
-
(1999)
IEEE Trans. Comput. Aided Des. Integrated Circuits Syst.
, vol.18
, Issue.7
, pp. 973-993
-
-
Marculescu, R.1
Marculescu, D.2
Pedram, M.3
-
19
-
-
0002425879
-
Loopy belief propagation for approximate inference: An empirical study
-
MURPHY, K. P., WEISS, Y., AND JORDAN, M. I. 1999. Loopy belief propagation for approximate inference: An empirical study. In Proceedings of the Conference on Uncertainty in AI, 467-475.
-
(1999)
Proceedings of the Conference on Uncertainty in AI
, pp. 467-475
-
-
Murphy, K.P.1
Weiss, Y.2
Jordan, M.I.3
-
20
-
-
0029230828
-
Power estimation in sequential circuits
-
NAJM, F., GOEL, S., AND HAJJ, I. 1995. Power estimation in sequential circuits. In Proceedings of the 32nd ACM/IEEE Design Automation Conference, 635-680.
-
(1995)
Proceedings of the 32nd ACM/IEEE Design Automation Conference
, pp. 635-680
-
-
Najm, F.1
Goel, S.2
Hajj, I.3
-
21
-
-
0027544156
-
Transition density: A new measure of activity in digital circuits
-
NAJM, F. N. 1993. Transition density: A new measure of activity in digital circuits. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 12, 2 (Feb.), 310-323.
-
(1993)
IEEE Trans. Comput. Aided Des. Integrated Circuits Syst.
, vol.12
, Issue.2 FEB
, pp. 310-323
-
-
Najm, F.N.1
-
22
-
-
1542359159
-
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
-
NGUYEN, D., DAVARE, A., ORSHANSKY, M., CHINNERY, D., THOMPSON, B., AND KEUTZER, K. 2003. Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. In Proceedings of the International Symposium on Low Power Electronics and Design, 158-163.
-
(2003)
Proceedings of the International Symposium on Low Power Electronics and Design
, pp. 158-163
-
-
Nguyen, D.1
Davare, A.2
Orshansky, M.3
Chinnery, D.4
Thompson, B.5
Keutzer, K.6
-
25
-
-
33750588360
-
A timing-aware probabilistic model for single-event-upset analysis
-
REJIMON, T. AND BHANJA, S. 2006. A timing-aware probabilistic model for single-event-upset analysis. IEEE Trans. VLSI Syst.
-
(2006)
IEEE Trans. VLSI Syst.
-
-
Rejimon, T.1
Bhanja, S.2
-
26
-
-
0036660316
-
Estimation of state line statistics in sequential circuits
-
SAXENA, V., NAJM, F. N., AND HAJJ, I. N. 2002. Estimation of state line statistics in sequential circuits. ACM Trans. Des. Autom. Electron. Syst. 7, 3, 455-473.
-
(2002)
ACM Trans. Des. Autom. Electron. Syst.
, vol.7
, Issue.3
, pp. 455-473
-
-
Saxena, V.1
Najm, F.N.2
Hajj, I.N.3
-
27
-
-
4444327756
-
Power minimization using simultaneous gate sizing, dual-vdd and dual-vth assignment
-
SRIVASTAVA, A., SYLVESTER, D., AND BLAAUW, D. 2004. Power minimization using simultaneous gate sizing, dual-vdd and dual-vth assignment. In Proceedings of the Design Automation Conference, 783-787.
-
(2004)
Proceedings of the Design Automation Conference
, pp. 783-787
-
-
Srivastava, A.1
Sylvester, D.2
Blaauw, D.3
-
28
-
-
0029698689
-
A Monte-Carlo approach for the accurate and efficient estimation of average transition probabilities in sequential logic circuits
-
STAMOULIS, G. I. 1996. A Monte-Carlo approach for the accurate and efficient estimation of average transition probabilities in sequential logic circuits. In Proceedings of the IEEE Custom Integrated Circuits Conference, 221-224.
-
(1996)
Proceedings of the IEEE Custom Integrated Circuits Conference
, pp. 221-224
-
-
Stamoulis, G.I.1
-
29
-
-
0029379466
-
Power estimation methods for sequential logic circuits
-
Tsui, C. Y., MONTEIRO, J., PEDRAM, M., DEVADAS, S., DESPAIN, A. M., AND LIN, B. 1995. Power estimation methods for sequential logic circuits. IEEE Trans. VLSI Syst. 3, 3, 404-416.
-
(1995)
IEEE Trans. VLSI Syst.
, vol.3
, Issue.3
, pp. 404-416
-
-
Tsui, C.Y.1
Monteiro, J.2
Pedram, M.3
Devadas, S.4
Despain, A.M.5
Lin, B.6
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