Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits

Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005

Volumn 2005, Issue , 2005, Pages 35-40

  Dhillon, Yuvraj S ^a   Diril, Abdulkadir U ^a   Chatterjee, Abhijit ^a   Metra, Cecilia ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; ERROR DETECTION; LOGIC DEVICES; NANOTECHNOLOGY; OPTIMIZATION; THRESHOLD VOLTAGE;

CO-OPTIMIZATION; PRIMARY OUTPUTS (PO); TECHNOLOGY SCALING; TRANSIENT ERRORS;

CMOS INTEGRATED CIRCUITS;

EID: 33745500660     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.41     Document Type: Conference Paper

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