Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

IEEE Transactions on Electron Devices

Volumn 53, Issue 5, 2006, Pages 1021-1029

  Åberg, Ingvar ^a   Chléirigh, Cáit Ní ^a   Hoyt, Judy L ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

Mobility; MOSFETs; Silicon germanium; Silicon on insulator (SOI); Strain

Indexed keywords

CARRIER CONCENTRATION; ELECTRON MOBILITY; ELECTROSTATICS; GATES (TRANSISTOR); HETEROJUNCTIONS; HOLE MOBILITY; LEAKAGE CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; STRAIN;

DOUBLE-GATE STRUCTURES; HETEROSTRUCTURE-ON-INSULATOR; STRAIN LEVEL; ULTRATHIN-BODY (UTB);

MOSFET DEVICES;

EID: 33646068335     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.871847     Document Type: Article

References (31)

1. T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, "A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors," in IEDM Tech. Dig., 2003, pp. 978-980.
2. S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, "A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films," in IEDM Tech. Dig., 2004, pp. 213-216.
3. J. M. Hinckley and J. Sing, "Influence of substrate composition and crystallographic orientation on the band structure of pseudomorphic Si-Ge alloy films," Phys. Rev. B, Condens. Matter, vol. 42, no. 6, pp. 3546-3566, Aug. 1990.
4. S. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, "Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 80, no. 3, pp. 1567-1577, Aug. 1996.
5. K. Rim, J. Chu, H. Chen, K. A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. Wong, "Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs," in VLSI Symp. Tech. Dig., 2002, pp. 98-99.
6. R. Oberhuber, G. Zandler, and P. Vogl, "Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET's," Phys. Rev. B, Condens. Matter, vol. 58, no. 15, pp. 9941-9948, Oct. 1998.
7. M. L. Lee and E. A. Fitzgerald, "Optimized strained Si/strained Ge dual-channel heterostructures for high mobility p- and n-MOSFETs," in IEDM Tech. Dig., 2003, pp. 429-432.
8. x (x < y) virtual substrates," Appl. Phys. Lett., vol. 79, no. 25, pp. 4246-4248, Dec. 2001.
9. x (x < y) virtual substrate," IEEE Electron Device Lett., vol. 24, no. 7, pp. 460-462, Jul. 2003.
10. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
11. C. Ni Chleirigh, O. O. Olubuyide, and J. L. Hoyt, "Mobility and sub-threshold characteristics in high-mobility dual-channel strained Si/ strained SiGe p-MOSFETs," in Proc. IEEE DRC, 2005, pp. 203-204.
12. K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, "Fabrication and mobility characteristics of ultrathin strained Si directly on insulator (SSDOI) MOSFETs," in IEDM Tech. Dig., 2003, pp. 47-52.
13. I. Åberg, O. O. Olubuyide, C. Ní Chléirigh, I. Lauer, D. A. Antoniadis, J. Li, R. Hull, and J. L. Hoyt, "Electron and hole mobility enhancements in sub-10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-back technique," in VLSI Symp. Tech. Dig., 2004, pp. 52-53.
14. I. Åberg, O. O. Olubuyide, J. Li, R. Hull, and J. L. Hoyt, "Fabrication of strained Si/strained SiGe/strained Si heterostructures on insulator by a bond and etch-back technique," in Proc. IEEE Int. SOI Conf., 2004, pp. 35-36.
15. T. S. Drake, C. Ní Chléirigh, M. L. Lee, A. J. Pitera, E. A. Fitzgerald, D. A. Antoniadis, D. H. Anjum, J. Li, R. Hull, N. Klymko, and J. L. Hoyt, "Fabrication of ultrathin strained silicon on insulator," J. Electron. Mater., vol. 32, no. 9, pp. 972-975, Sep. 2003.
16. D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2842-2850, Dec. 2001.
17. H. M. Nayfeh, J. L. Hoyt, and D. A. Antoniadis, "A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2069-2072, Dec. 2004.
18. S. Yu, J. Jung, J. L. Hoyt, and D. A. Antoniadis, "Strained-Si-strained-SiGe dual-channel layer structure as CMOS substrate for single workfunction metal-gate technology," IEEE Electron Device Lett., vol. 25, no. 6, pp. 402-404, Jun. 2004.
19. J. Jung, C. Ni Chleirigh, S. Yu, O. O. Olubuyide, J. Hoty, and D. A. Antoniadis, "Tradeoff between mobility and subthreshold characteristics in dual-channel heterostructure n- and p-MOSFETs," IEEE Electron Device Lett., vol. 25, no. 8, pp. 562-564, Aug. 2004.
20. I. Åberg, C. Ní Chléirigh, O. O. Olubuyide, X. Duan, and J. L. Hoyt, "High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si heterostructures on insulator," in IEDM Tech. Dig., 2004, pp. 173-176.
21. Dessis: Comprehensive Semiconductor Device Simulator, Zurich, Switzerland: Integrated Systems Engineering AG. [Online]. Available: http://www.ise.com
22. x dual-channel enhanced mobility structures," in Proc. ECS: SiGe: Mater., Processing Device, 2004, vol. PV2004-7, pp. 99-109.
23. J. Jung, S. Yu, M. L. Lee, J. L. Hoyt, E. A. Fitzgerald, and D. A. Antoniadis, "Mobility enhancement in dual-channel p-MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1424-1431, Sep. 2004.
24. S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, and T. Maeda, "Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained SOI) MOSFETs," in IEDM Tech. Dig., 2003, pp. 57-60.
25. I. Åberg, C. Ni Chleirigh, and J. L. Hoyt, "Thermal processing and mobility in strained heterostructures on insulator," in Proc. ECS: Adv. Gate Stack, Source/Drain Channel Eng. Si-Based CMOS: New Mater., Processes, Equip., 2005, vol. PV2005-05, pp. 505-514.
26. Y-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," IEEE Electron Device Lett., vol. 21, no. 5, pp. 254-555, May 2000.
27. I. Aberg and J. L. Hoyt, "Hole transport in ultrathin body MOSFETs in strained silicon directly on insulator with strained silicon thickness less than 5 nm," IEEE Electron Device Lett., vol. 26, no. 9, pp. 661-663, Sep. 2005.
28. K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, "Experimental study on carrier transport mechanism in ultrathin body n- and p-MOSFETs with SOI thickness less than 5 nm," in IEDM Tech. Dig., 2002, pp. 47-50.
29. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K. C. Saraswat, "Low defect ultrathin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT)," in VLSI Symp. Tech. Dig., 2005, pp. 82-83.
30. G. Xia, H. M. Nayfeh, M. L. Lee, E. A. Fitzgerald, D. A. Antoniadis, D. H. Anjum, J. Li, R. Hull, N. Klymko, and J. L. Hoyt, "Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si n-channel MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2136-2144, Dec. 2004.
31. 2/TiN gate stack down to 15 nm gate length," in Proc. IEEE Int. SOI Conf. Tech. Dig., 2005, pp. 223-225.