Efficient pattern mapping for deterministic logic BIST

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 48-56

  Gherman, Valentin ^a   Wunderlich, Hans Joachim ^a   Vranken, Harald ^b   Hapke, Friedrich ^c   Wittke, Michael ^c   Garbers, Michael ^c  

^a UNIVERSITY OF STUTTGART   (Germany)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

BDDs; Logic BIST

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; COMPUTER HARDWARE; INTEGRATED CIRCUITS; POLYNOMIALS;

BINARY DECISION DIAGRAMS (BDD); CORE UNDER TEST (CUT); LOGIC BIST; PSEUDO-RANDOM PATTERNS;

LOGIC CIRCUITS;

EID: 18144422473     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. S.B. Akers "Binary Decision Diagrams," IEEE Transactions on Computers, Vol. C-27, No. 6, June 1978, pp. 509-516.
2. R.E. Bryant "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, C-35-8, August 1986, pp. 677-691.
3. R.K. Brayton, G.D. Hachtel, C.T. McMullen and A.L. Sangiovanni- Vincentelli "Logic Minimization Algorithms for VLSI Synthesis," Kluver Academic Publishers, 1997.
4. M.J. Geuzebroek, J.Th. van der Linden, A.J. van de Goor "Test Point Insertion for Compact Test Sets," Proceedings of International Test Conference, IEEE, 2000, pp. 506-514.
5. J.P. Hayes, A.D. Friedman "Test Point Placement to Simplify Fault Detection," IEEE Transactions on Computers, Vol. C-33, July 1974, pp. 727-735.
6. S. Hellebrand, S. Tarnik, J. Rajski, B. Courtois "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," Proceedings of International Test Conference, 1992, pp. 120-129.
7. S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich "Pattern Generation for a Deterministic BIST Scheme," Proceedings ACM/IEEE International Conference on CAD-95 (ICCAD95), San Jose, CA, November 1995, pp. 88-94.
8. H. Liang, S. Hellebrand, H.-J. Wunderlich "Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST," Proceedings IEEE International Test Conference, Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April 2002, pp. 157-168.
9. G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, J. Rajski "Logic BIST for Large Industrial Designs: Real Issues and Case Studies," Proceedings of International Test Conference, IEEE, 1999, pp. 358-367.
10. G. Kiefer, H. Vranken, E. J. Marinissen, H.-J. Wunderlich "Application of Deterministic Logic BIST on Industrial Circuits, " Proceedings IEEE International Test Conference, ITC 2000, Atlantic City, NJ, October 3-5, 2000, pp. 105-114.
11. G. Kiefer, H.-J. Wunderlich "Using BIST Control for Pattern Generation," Proceedings International Test Conference, IEEE, 1997, pp. 347-355.
12. G. Kiefer, H.-J. Wunderlich "Deterministic BIST with Multiple Scan Chains," Proceedings International Test Conference, IEEE, 1998, pp. 1057-1064.
13. B. Koenemann "LFSR-Coded Test Patterns for Scan Designs," Proceedings of European Test Conference, 1991, pp. 237-242.
14. J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.-H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski, G. Eide, J. Qian "Embedded deterministic test for low cost manufacturing test", Proceedings of International Test Conference, IEEE, 2002, pp. 301-310.
15. B. H. Seiß, P. M. Trouborst and M. H. Schulz "Test Point Insertion for Scan-Based BIST," European Test Conference (ETC), April 1991, pp. 253-262.
16. N. A. Touba, and E. J. McCluskey "Altering a pseudo- random bit sequence for scan-based BIST," Proceedings IEEE International Test Conference, 1996, pp. 167-175.
17. H. Vranken, F. Meister, H.-J. Wunderlich "Combining Deterministic Logic BIST with Test Point Insertion," The Seventh IEEE European Test Workshop, May 26-29, 2002.
18. H. Vranken, H.-J. Wunderlich, F. Syafei Sapei "Impact of Test Point Insertion on Silicon Area and Timing During Layout," Design, Automation and Test in Europe, Paris, 16-20 February 2004.
19. H.-J. Wunderlich, G. Kiefer "Bit-Flipping BIST," Proceedings International Conference on Computer Aided Design, IEEE, 1996, pp. 337-343.
20. H.-J. Wunderlich "BIST for Systems-on-a-Chip," INTEGRATION, the VLSI journal, 1998, pp. 57-78.
21. http://vlsi.colorado.edu/~fabio/CUDD/cuddIntro.html