Compact test sets for high defect coverage

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 8, 1997, Pages 923-930

  Reddy, Sudhakar M ^a   Pomeranz, Irith ^a   Kajihara, Seiji ^b  

^a University of Iowa   (United States)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; HEURISTIC METHODS;

DEFECT COVERAGES;

INTEGRATED CIRCUIT TESTING;

EID: 0031198751     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.644620     Document Type: Article

References (17)

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