-
1
-
-
0346781606
-
"A review of electrostatic discharge (ESD) in advanced semiconductor technology"
-
S. H. Voldman, "A review of electrostatic discharge (ESD) in advanced semiconductor technology," Microelectron. Reliab., vol. 44, pp. 33-46, 2004.
-
(2004)
Microelectron. Reliab.
, vol.44
, pp. 33-46
-
-
Voldman, S.H.1
-
2
-
-
11344291343
-
"A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD"
-
S. H. Voldman, "A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD," Microelectron. Reliab., vol. 45, pp. 323-340, 2005.
-
(2005)
Microelectron. Reliab.
, vol.45
, pp. 323-340
-
-
Voldman, S.H.1
-
3
-
-
15744385079
-
"A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) silicon germanium technologies: Part II-ESD"
-
S. H. Voldman, "A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) silicon germanium technologies: Part II-ESD," Microelectron. Reliab., vol. 45, pp. 437-455, 2005.
-
(2005)
Microelectron. Reliab.
, vol.45
, pp. 437-455
-
-
Voldman, S.H.1
-
4
-
-
0032204363
-
"ESD protection techniques for high frequency integrated circuits"
-
G. Croft and J. Bernier, "ESD protection techniques for high frequency integrated circuits," Microelectron. Reliab., vol. 38, pp. 1681-1689, 1998.
-
(1998)
Microelectron. Reliab.
, vol.38
, pp. 1681-1689
-
-
Croft, G.1
Bernier, J.2
-
5
-
-
0002140154
-
"Using SCRs as transient protection structures in integrated circuits"
-
L. Avery, "Using SCRs as transient protection structures in integrated circuits," in Proc. EOS/ESD Symp., 1983, pp. 177-180.
-
(1983)
Proc. EOS/ESD Symp.
, pp. 177-180
-
-
Avery, L.1
-
6
-
-
0024176693
-
"A process tolerant input protection circuit for advanced CMOS processes"
-
R. Rountree, C. Duvvury, T. Maki, and H. Stiegler, "A process tolerant input protection circuit for advanced CMOS processes," in Proc. EOS/ESD Symp., 1988, pp. 201-211.
-
(1988)
Proc. EOS/ESD Symp.
, pp. 201-211
-
-
Rountree, R.1
Duvvury, C.2
Maki, T.3
Stiegler, H.4
-
7
-
-
0025953251
-
"A low-voltage triggering SCR for on-chip ESD protection at output and input pads"
-
Jan
-
A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol. 12, no. 1, pp. 21-22, Jan. 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, Issue.1
, pp. 21-22
-
-
Chatterjee, A.1
Polgreen, T.2
-
8
-
-
11544252530
-
"Dual rail ESD protection using complementary SCRs"
-
G. Croft, "Dual rail ESD protection using complementary SCRs," in Proc. EOS/ESD Symp., 1992, pp. 243-249.
-
(1992)
Proc. EOS/ESD Symp.
, pp. 243-249
-
-
Croft, G.1
-
9
-
-
0343199852
-
"A novel CMOS ESD/EOS protection circuit with full SCRs structures"
-
M.-D. Ker, C. Wu, and C. Lee, "A novel CMOS ESD/EOS protection circuit with full SCRs structures," in Proc. EOS/ESD Symp., 1992, pp. 258-264.
-
(1992)
Proc. EOS/ESD Symp.
, pp. 258-264
-
-
Ker, M.-D.1
Wu, C.2
Lee, C.3
-
10
-
-
0030836964
-
"A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep sub-micron low voltage CMOS IC"
-
Jan
-
M.-D. Ker, H.-H. Chang, and C.-Y. Wu, "A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep sub-micron low voltage CMOS IC," IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 38-51, Jan. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.1
, pp. 38-51
-
-
Ker, M.-D.1
Chang, H.-H.2
Wu, C.-Y.3
-
11
-
-
0031249221
-
"Using an SCR as ESD protection without latch-up danger"
-
G. Notermans, F. Kuper, and J. Luchies, "Using an SCR as ESD protection without latch-up danger," Microelectron. Reliabil., vol. 37, pp. 1457-1460, 1997.
-
(1997)
Microelectron. Reliabil.
, vol.37
, pp. 1457-1460
-
-
Notermans, G.1
Kuper, F.2
Luchies, J.3
-
12
-
-
0011003950
-
"Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in sub-micron CMOS technology"
-
Jul
-
M.-D. Ker, "Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in sub-micron CMOS technology," IEEE Trans. Electron Devices, vol. 45, no. 7, pp. 849-860, Jul. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, Issue.7
, pp. 849-860
-
-
Ker, M.-D.1
-
13
-
-
0034159376
-
"Cascode LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger"
-
M.-D. Ker and H.-H. Chang, "Cascode LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger," Solid-State Electron., vol. 44, pp. 425-445, 2000.
-
(2000)
Solid-State Electron.
, vol.44
, pp. 425-445
-
-
Ker, M.-D.1
Chang, H.-H.2
-
14
-
-
0035339705
-
"On a dual-polarity on-chip electrostatic discharge protection structure"
-
Aug
-
A. Wang and C.-H. Tsay, "On a dual-polarity on-chip electrostatic discharge protection structure," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 978-984, Aug. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.8
, pp. 978-984
-
-
Wang, A.1
Tsay, C.-H.2
-
15
-
-
1042280058
-
"New ESD protection circuits based on PNP triggering SCR for advanced CMOS device applications"
-
Y. Morishita, "New ESD protection circuits based on PNP triggering SCR for advanced CMOS device applications," in Proc. EOS/ESD Symp., 2002, p. 1A.2.
-
(2002)
Proc. EOS/ESD Symp.
-
-
Morishita, Y.1
-
16
-
-
5444275024
-
"High holding current SCRs (HHI-SCR) for ESD protection and latchup immune IC operation"
-
M. P. J. Mergens, C. C. Russ, J. Armer, P. C. Jozwiak, and R. Mohn, "High holding current SCRs (HHI-SCR) for ESD protection and latchup immune IC operation," in Proc. EOS/ESD Symp., 2002, p. 1A.3.
-
(2002)
Proc. EOS/ESD Symp.
-
-
Mergens, M.P.J.1
Russ, C.C.2
Armer, J.3
Jozwiak, P.C.4
Mohn, R.5
-
17
-
-
3042562496
-
"SCR device with double-triggered technique for on-chip ESD protection in sub-quatter-micron silicided CMOS processes"
-
Jan
-
M.-D. Ker and K. C. Hsu, "SCR device with double-triggered technique for on-chip ESD protection in sub-quatter-micron silicided CMOS processes," IEEE Trans. Device Mater Reliab., vol. 3, no. 1, pp. 58-68, Jan. 2003.
-
(2003)
IEEE Trans. Device Mater Reliab.
, vol.3
, Issue.1
, pp. 58-68
-
-
Ker, M.-D.1
Hsu, K.C.2
-
18
-
-
0037226523
-
"LVTSCR structure for latch-up free ESD protection of BiCMOS RF circuits"
-
V. Vashchenko, A. Concannon, M. Ter Beek, and P. Hopper, "LVTSCR structure for latch-up free ESD protection of BiCMOS RF circuits," Microelectron. Reliab., vol. 43, pp. 61-69, 2003.
-
(2003)
Microelectron. Reliab.
, vol.43
, pp. 61-69
-
-
Vashchenko, V.1
Concannon, A.2
Ter Beek, M.3
Hopper, P.4
-
19
-
-
5444248675
-
"SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-μm fully salicided CMOS process"
-
Oct
-
M.-D. Ker and Z.-P. Chen, "SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-μm fully salicided CMOS process," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1731-1733, Oct. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.10
, pp. 1731-1733
-
-
Ker, M.-D.1
Chen, Z.-P.2
-
20
-
-
4444372557
-
"Novel and robust silicon controlled rectifier (SCR) based devices for on-chip ESD protection"
-
Jun
-
J. A. Salcedo, J. J. Liou, and J. C. Bernier, "Novel and robust silicon controlled rectifier (SCR) based devices for on-chip ESD protection," IEEE Electron Device Lett., vol. 25, no. 6, p. 658, Jun. 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.6
, pp. 658
-
-
Salcedo, J.A.1
Liou, J.J.2
Bernier, J.C.3
-
22
-
-
14844331453
-
"Novel and robust Silicon Controlled Rectifier (SCR) based devices for on-chip ESD protection"
-
J. A. Salcedo, J. J. Liou, and J. C. Bernier, "Novel and robust Silicon Controlled Rectifier (SCR) based devices for on-chip ESD protection," in Proc. 11th IEEE Int. Symp. Physical Failure Analysis Integrated Circuits, 2004, pp. 75-80.
-
(2004)
Proc. 11th IEEE Int. Symp. Physical Failure Analysis Integrated Circuits
, pp. 75-80
-
-
Salcedo, J.A.1
Liou, J.J.2
Bernier, J.C.3
-
24
-
-
29244473225
-
"Two-dimensional process simulation program"
-
ATHENA/SSUPREM 4, Silvaco International, Santa Clara, CA
-
ATHENA/SSUPREM 4, "Two-dimensional process simulation program," Silvaco International, Santa Clara, CA, 2004.
-
(2004)
-
-
-
25
-
-
84946491991
-
Two-dimensional device simulation program
-
ATLAS, Silvaco International, Santa Clara, CA
-
ATLAS, Two-dimensional device simulation program, Silvaco International, Santa Clara, CA, 2004.
-
(2004)
-
-
|