Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

IEEE Transactions on Electron Devices

Volumn 45, Issue 4, 1998, Pages 849-860

  Ming Dou Ker, ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL NOISE; LOW VOLTAGE HIGH CURRENTS; NORMAL OPERATING CONDITIONS; PROCESS MODIFICATIONS; SUB-MICRON CMOS TECHNOLOGY; TRIGGER CURRENTS; TRIGGER VOLTAGE; TRIGGERING CHARACTERISTICS;

CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE;

MOS DEVICES;

EID: 0011003950     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.662790     Document Type: Article

References (29)

1. C. Duvvury, R. N. Rountree, Y. Fong, and R. A. McPhee, "ESD phenomena and protection issues in CMOS output buffers," in Proc. IRPS, 1987, pp. 174-180.
2. C. Duvvury and A. Amerasekera, "ESD: A pervasive reliability concern for IC technologies," Proc. IEEE, vol. 81, pp. 690-702, May 1993.
3. A. Amerasekera and C. Duvvury, "The impact of technology scaling on ESD robustness and protection circuit design," in 1994 EOS/ESD Symp. Proc., vol. EOS-16, pp. 237-245.
4. C. Duvvury, R. McPhee, D. Baglee, and R. Rountree, "ESD protection in 1-m CMOS technologies," in Proc. IRPS, 1986, pp. 199-205.
5. R. N. Rountree, "ESD protection for submicron CMOS circuits: issues and solutions," in IEDM Tech. Dig., 1988, pp. 580-583.
6. C. Duvvury and R. N. Rountree, "A synthesis of ESD input protection scheme," in 1991 EOS/ESD Symp. Proc., vol. EOS-13, pp. 88-97.
7. C.-Y. Wu, M.-D. Ker, C.-Y. Lee, and J. Ko, "A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI," IEEE J. Solid-State Circuits, vol. 27, pp. 274-280, 1992.
8. M.-D. Ker and C.-Y. Wu, "Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's," IEEE Trans. Electron Devices, vol. 42, pp. 1297-1304, July 1995.
9. M.-D. Ker, C.-Y. Wu, T. Cheng, M. Wu, T.-L. Yu, and A. Wang, "Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins," in Proc. 1994 IEEE Int. Integrated Reliab. Workshop, pp. 124-128.
10. A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for onchip ESD protection at output and input pads," in 1990 Proc. Symp. VLSI Technol., pp. 75-76.
11. , "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol. 12, pp. 21-22, Jan. 1991.
12. M.-D. Ker, K.-F. Wang, M.-C. Joe, Y.-H. Chu, and T.-S. Wu, "Areaefficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC," in Proc. 8th IEEE Int. ASIC Conf. and Exhibit, 1995, pp. 123-126.
13. M.-D. Ker, C.-Y. Wu, and H.-H. Chang, "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, vol. 43, pp. 588-598, Apr. 1996.
14. C. Diaz and G. Motley, "Bi-modal triggering for LVSCR ESD protection devices," in 1994 EOS/ESD Symp. Proc., vol. EOS-16, pp. 106-112.
15. Electromagnetic Compatibility for Industrial-Process Measurement and Control Equipment, Int. Standard IEC 801-2, 1991.
16. M. B. Corp, ZZAAP!: Taming ESD, RFI, and EMI. New York: Academic, 1990.
17. J. S. Maas and D. A. Skjeie, "Testing electronic products for susceptibility to electrostatic discharge," in Proc. EOS/ESD Symp., 1990, vol. EOS-12, pp. 92-96.
18. W. T. Rhoades, "ESD stress on IC's in equipment," in Proc. EOS/ESD Symp., 1990, vol. EOS-12, pp. 82-91.
19. R. Lewis and J. Minor, "Simulation of a system level transient-induced latchup event," in Proc. EOS/ESD Symp., 1994, vol. EOS-16, pp. 193-199.
20. E. Chwastek, "A new method for assessing the susceptibility of CMOS integrated circuits to latch-up: the system-transient technique," in Proc. EOS/ESD Symp., 1989, vol. EOS-11, pp. 149-155.
21. G. Weiss and D. Young, "Transient-induced latchup testing of CMOS integrated circuits," in Proc. EOS/ESD Symp., 1995, vol. EOS-17, pp. 194-198.
22. M.-D. Ker, "ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices," in Proc. IEEE Int. ASIC Conf. and Exhibits, 1997, pp. 283-286.
23. D. B. Scott, P. W. Bosshart, and J. D. Gallia, "Circuit to improve electrostatic discharge protection," U.S. Patent 5 019 888, 1991.
24. G. N. Roberts, "Output ESD protection circuit," U.S. Patent 5 218 222, 1993.
25. K. F. Lee, A. Lee, M. L. Marmet, and K. W. Ouyang, "Electro-static discharge protection circuit with bimodal resistance characteristics," U.S. Patent 5 270 565, 1993.
26. M.-D. Ker and C.-Y. Wu, "Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method: Part I- theoretical derivation," IEEE Trans. Electron Devices, vol. 42, pp. 1141-1148, June 1995.
27. , "Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method: Part II- Quantitative evaluation," IEEE Trans. Electron Devices, vol. 42, pp. 1149-1155, June 1995.
28. ESD Testing For IC's, 2nd ed., KeyTek Instrument Corp., 1990.
29. Instruction Manual for ThermoChuck Systems, Temptronic Corporation, 1987.