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Retrograde well and epitaxial thickness optimization for shallow- and deep-trench collar merged isolation and node Trench SPT cell and CMOS logic technology
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A transmission line pulse (TLP) picosecond imaging circuit analysis (PICA) methodology for evaluation of ESD and latchup
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Latchup Session May
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A new I/O signal latchup phenomenon in voltage tolerance ESD protection circuits
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Deep trench guard ring structures and evaluation of the probability of minority carrier escape for ESD and latchup in advanced BiCMOS SiGe technology
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National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13
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Watson A, Voldman S, Larsen T. Deep trench guard ring structures and evaluation of the probability of minority carrier escape for ESD and latchup in advanced BiCMOS SiGe technology. In: Proceedings of the Taiwan electrostatic discharge conference. National Chiao-Tung University, Hsin-chu City, Taiwan, November 12-13, 2003. p. 97-103
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The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS Silicon Germanium technology
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28744443921
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Influence of silicon dioxide-filled trench isolation (TI) structure and implanted sub-collector on latchup robustness
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Latchup in merged triple well technology
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