Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger

Solid-State Electronics

Volumn 44, Issue 3, 2000, Pages 425-445

  Ker, Ming Dou ^a   Chang, Hun Hsien ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; ELECTROSTATICS; INTEGRATED CIRCUIT MANUFACTURE; MASKS; MOS DEVICES; SEMICONDUCTING SILICON; SPURIOUS SIGNAL NOISE; TEMPERATURE;

ELECTROSTATIC DISCHARGE; NOISE PULSES; SILICIDE; TUNABLE HOLDING VOLTAGE;

THYRISTORS;

EID: 0034159376     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(99)00247-6     Document Type: Article

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