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Volumn 3, Issue 3, 2003, Pages 58-68

SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

Author keywords

Double triggered technique; Electrostatic discharge (ESD); ESD protection circuit; Silicon controlled rectifier (SCR)

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC DISCHARGES; ELECTRIC RECTIFIERS; ELECTROSTATICS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; SILICON; SWITCHING;

EID: 3042562496     PISSN: 15304388     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDMR.2003.815192     Document Type: Article
Times cited : (26)

References (16)
  • 1
    • 0024174395 scopus 로고
    • ESD protection for submicron CMOS circuits: Issues and solutions
    • R. Rountree, "ESD protection for submicron CMOS circuits: Issues and solutions," in IEDM Tech. Dig., 1988, pp. 580-583.
    • (1988) IEDM Tech. Dig. , pp. 580-583
    • Rountree, R.1
  • 2
    • 0032273088 scopus 로고    scopus 로고
    • Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: An overview
    • M.-D. Ker, "Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: An overview," in Proc. IEEE Int. Conf. Electronic Circuits and Systems, 1998, pp. 325-328.
    • (1998) Proc. IEEE Int. Conf. Electronic Circuits and Systems , pp. 325-328
    • Ker, M.-D.1
  • 3
    • 0027883867 scopus 로고
    • ESD protection of BiCMOS integrated circuits which need to operate in the harsh environments of automotive or industrial
    • M. Corsi, R. Nimmo, and F. Fattori, "ESD protection of BiCMOS integrated circuits which need to operate in the harsh environments of automotive or industrial," in Proc. EOS/ESD Symp., 1993, pp. 209-213.
    • (1993) Proc. EOS/ESD Symp. , pp. 209-213
    • Corsi, M.1    Nimmo, R.2    Fattori, F.3
  • 4
    • 0031249221 scopus 로고    scopus 로고
    • Using an SCR as ESD protection without latch-up danger
    • G. Notermans, F. Kuper, and J. M. Luchis, "Using an SCR as ESD protection without latch-up danger," Microelectron. Reliabil., vol. 37, pp. 1457-1460, 1997.
    • (1997) Microelectron. Reliabil. , vol.37 , pp. 1457-1460
    • Notermans, G.1    Kuper, F.2    Luchis, J.M.3
  • 5
    • 0011003950 scopus 로고    scopus 로고
    • Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology
    • Apr.
    • M.-D. Ker, "Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology," IEEE Trans. Electron Devices, vol. 45, pp. 849-860, Apr. 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , pp. 849-860
    • Ker, M.-D.1
  • 6
    • 0025953251 scopus 로고
    • A low-voltage triggering SCR for on-chip ESD protection at output and input pads
    • Jan.
    • A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol. 12, pp. 21-22, Jan. 1991.
    • (1991) IEEE Electron Device Lett. , vol.12 , pp. 21-22
    • Chatterjee, A.1    Polgreen, T.2
  • 7
    • 0032597591 scopus 로고    scopus 로고
    • How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on
    • M.-D. Ker and H.-H. Chang, "How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on," J. Electrostatics, vol. 47, pp. 215-248, 1999.
    • (1999) J. Electrostatics , vol.47 , pp. 215-248
    • Ker, M.-D.1    Chang, H.-H.2
  • 8
    • 84948982831 scopus 로고    scopus 로고
    • GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes
    • C. Russ, M. Mergens, J. Armer, P. Jozwiak, G. Kolluri, L. Avery, and K. Verhaege, "GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes," in Proc. EOS/ESD Symp., 2001, pp. 22-31.
    • (2001) Proc. EOS/ESD Symp. , pp. 22-31
    • Russ, C.1    Mergens, M.2    Armer, J.3    Jozwiak, P.4    Kolluri, G.5    Avery, L.6    Verhaege, K.7
  • 9
    • 0009558710 scopus 로고
    • Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method - Part I: Theoretical derivation
    • June
    • M.-D. Ker and C.-Y. Wu, "Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method - Part I: Theoretical derivation," IEEE Trans. Electron Devices, vol. 42, pp. 1141-1148, June 1995.
    • (1995) IEEE Trans. Electron Devices , vol.42 , pp. 1141-1148
    • Ker, M.-D.1    Wu, C.-Y.2
  • 12
    • 0030128946 scopus 로고    scopus 로고
    • Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
    • Apr.
    • M.-D. Ker, C.-Y. Wu, and H.-H. Chang, "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, vol. 43, pp. 588-598, Apr. 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , pp. 588-598
    • Ker, M.-D.1    Wu, C.-Y.2    Chang, H.-H.3
  • 14
    • 0032740282 scopus 로고    scopus 로고
    • SS ESD clamp circuits for submicron CMOS VLSI
    • Jan.
    • SS ESD clamp circuits for submicron CMOS VLSI," IEEE Trans. Electron Devices, vol. 46, pp. 173-183, Jan. 1999.
    • (1999) IEEE Trans. Electron Devices , vol.46 , pp. 173-183
    • Ker, M.-D.1
  • 15
    • 0022212124 scopus 로고
    • Transmission line pulsing techniques for circuit modeling of ESD phenomena
    • T. J. Maloney and N. Khurana, "Transmission line pulsing techniques for circuit modeling of ESD phenomena," in Proc. EOS/ESD Symp., 1985, pp. 49-54.
    • (1985) Proc. EOS/ESD Symp. , pp. 49-54
    • Maloney, T.J.1    Khurana, N.2
  • 16


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.