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Volumn , Issue , 2004, Pages 75-80

Novel and Robust Silicon Controlled Rectifier (SCR) based devices for On-Chip ESD protection

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIODES; ELECTROCHEMISTRY; ELECTROSTATICS; MICROPROCESSOR CHIPS; OPTIMIZATION; RELIABILITY; ROBUSTNESS (CONTROL SYSTEMS); SILICON; VOLTAGE CONTROL;

EID: 14844331453     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (9)
  • 1
    • 0025953251 scopus 로고
    • A low-voltage triggering SCR for On-Chip ESD protection at output and input pads
    • Jan.
    • A. Chatterjee and T. Polgreen, "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", IEEE Electron Device Letters, vol. 12, pp. 21-22 Jan. 1991.
    • (1991) IEEE Electron Device Letters , vol.12 , pp. 21-22
    • Chatterjee, A.1    Polgreen, T.2
  • 2
    • 0035339705 scopus 로고    scopus 로고
    • On a dual-polarity on-chip electrostatic discharge protection structure
    • May
    • A. Z. H. Wang and C.-H. Tsay, "On a Dual-Polarity On-Chip Electrostatic Discharge Protection Structure", IEEE Trans. Electron Devices, vol. 48, pp. 978-984, May 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , pp. 978-984
    • Wang, A.Z.H.1    Tsay, C.-H.2
  • 3
    • 0034159376 scopus 로고    scopus 로고
    • Cascode LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
    • M.-D. Ker and H.-H. Chang, "Cascode LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger", Solid-State Electronics, vol. 44, pp. 425-445, 2000.
    • (2000) Solid-State Electronics , vol.44 , pp. 425-445
    • Ker, M.-D.1    Chang, H.-H.2
  • 4
    • 14844335575 scopus 로고    scopus 로고
    • "On-Chip structure for electrostatic discharge (ESD) protection", US Patent filed Jan.
    • J. A. Salcedo, J. J. Liou, J. C. Bernier, and D. K. Whitney, "On-Chip structure for electrostatic discharge (ESD) protection", US Patent filed Jan. 2004.
    • (2004)
    • Salcedo, J.A.1    Liou, J.J.2    Bernier, J.C.3    Whitney, D.K.4
  • 6
    • 14844282607 scopus 로고    scopus 로고
    • "High voltage Protection Circuits",US Patent 5,663,860, Sep.
    • J. W. Swonger, "High voltage Protection Circuits", US Patent 5,663,860, Sep. 1997.
    • (1997)
    • Swonger, J.W.1
  • 7
    • 0029408582 scopus 로고
    • Bi-Modal triggering for LVTSCR ESD protection devices
    • Nov.
    • C. Diaz, G. Motley, "Bi-Modal triggering for LVTSCR ESD protection devices", Journal of Electrostatic, vol. 36, pp. 3-17, Nov. 1995.
    • (1995) Journal of Electrostatic , vol.36 , pp. 3-17
    • Diaz, C.1    Motley, G.2
  • 8
    • 0036609869 scopus 로고    scopus 로고
    • Stacked N-MOS silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
    • June
    • M.-D. Ker, C.-H. Chuang, "Stacked N-MOS silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface", IEEE Electron Device Letters, vol. 23, pp. 363-365, June 2002.
    • (2002) IEEE Electron Device Letters , vol.23 , pp. 363-365
    • Ker, M.-D.1    Chuang, C.-H.2
  • 9
    • 0036568226 scopus 로고    scopus 로고
    • Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
    • May
    • M.-D. Ker, T.-Y. Cheng, C.-Y. Wu, "Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits", Solid-State Electronics, vol. 46, pp. 721-734, May 2002
    • (2002) Solid-State Electronics , vol.46 , pp. 721-734
    • Ker, M.-D.1    Cheng, T.-Y.2    Wu, C.-Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.