SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-μm fully salicided CMOS process

IEEE Transactions on Electron Devices

Volumn 51, Issue 10, 2004, Pages 1731-1733

  Ker, Ming Dou ^a   Chen, Zi Ping ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; ELECTROSTATICS; EQUIVALENT CIRCUITS; MICROPROCESSOR CHIPS; TRANSISTORS;

ELECTROSTATIC DISCHARGE; HOLDING CURRENT; HOLDING VOLTAGE; LATCH UP;

THYRISTORS;

EID: 5444248675     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.834904     Document Type: Article

References (16)

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