Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction

IEEE Computer Architecture Letters

Volumn 3, Issue 1, 2004, Pages 4-

  Stine, Jeffrey M ^a   Carter, Nicholas P ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 38348999288     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2004.5     Document Type: Article

References (6)

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3. J. Kim and M. Horowitz, “Adaptive supply serial links with sub-l-V operation and per-pin clock recovery,” Journal of Solid-State Circuits, vol. 37, pp. 1403–1413, Nov. 2002.
4. L. Shang, L.-S. Peh, and N. K. Jha, “Dynamic voltage scaling with links for power optimization of interconnection networks,” in International Solid-State Circuits Conference, Anaheim, CA, Feb. 2003, pp. 91–102.
5. G. Varatkar and R. Marculescu, “Traffic analysis for on-chip networks design of multimedia applications,” in 39th Conference on Design Automation, 2002, pp. 795–800.
6. F. Worm, P. Ienne, P. Thiran, and G. De Micheli, “An adaptive low-power transmission scheme for on-chip networks,” in International Symposium on System Synthesis, 2002, pp. 92–100