Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance?

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2001, Pages 62-71

  Cuppu, V ^a   Jacob, B ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONCURRENT ENGINEERING; DATA REDUCTION; INTERFACES (COMPUTER); QUEUEING THEORY;

LATENCY; SYSTEM OVERHEAD; UNIPROCESSOR;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034856730     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)

1. Operating system benchmarking in the wake of imbench: A case study of the performance of NetBSD on the Intel x86 architecture
2. A high-performance, low-cost multiprocessor bus for workstations and midrange servers
3. Impulse: Building a smarter memory controller
4. A performance comparison of contemporary DRAM architectures
5. The new DRAM interfaces: SDRAM, RDRAM and variants
6. DDR2 and low latency variants
7. Sony's emotionally charged chip: Killer floating-point 'Emotion engine' to power PlayStation 2000
8. DRAM redesign: Not just plastic surgery
9. The slammin, jammin, DRAM scramble
10. Alpha 21364 to ease memory bottleneck: Compaq will add direct RDRAM to 21264 core for late 2000 shipments
11. Access order and effective bandwidth for streams on a Direct Rambus memory
12. A new memory system design for commercial and technical computing products
13. Lockup-free instruction fetch/prefetch cache organization
14. Design and evaluation of dynamic access ordering hardware
15. Access ordering and memory-conscious cache utilization
16. MoSys reveals MDRAM architecture
17. Design of the 21174 memory controller for DIGITAL personal workstations
18. Increasing TLB reach using superpages backed by shadow memory
19. MoSys tries synthetic SRAM