Design of a parallel vector access unit for SDRAM memory systems

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 39-48

  Mathew, Binu K ^a   McKee, Sally A ^a   Carter, John B ^a   Davis, Al ^a  

^a UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SIMULATION; DATA STRUCTURES; DYNAMIC RANDOM ACCESS STORAGE; OPTIMIZATION; PERSONAL COMPUTERS; STATIC RANDOM ACCESS STORAGE; STORAGE ALLOCATION (COMPUTER); SUPERCOMPUTERS; VECTORS;

GATE LEVEL SIMULATION; PARALLEL VECTOR ACCESS UNIT; SMART MEMORY CONTROLLER; STATIC DYNAMIC RANDOM ACCESS STORAGE;

PARALLEL PROCESSING SYSTEMS;

EID: 0034581564     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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