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Volumn 2002-January, Issue , 2002, Pages 107-116

Fine-grain priority scheduling on multi-channel memory systems

Author keywords

Application software; Bandwidth; Computer science; Concurrent computing; Delay; Educational institutions; Processor scheduling; Random access memory; Resumes; System performance

Indexed keywords

APPLICATION PROGRAMS; BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; DYNAMIC RANDOM ACCESS STORAGE; MEMORY ARCHITECTURE; RANDOM ACCESS STORAGE; SCHEDULING; SUPERCOMPUTERS;

EID: 84949752992     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2002.995702     Document Type: Conference Paper
Times cited : (21)

References (21)
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    • 0034839064 scopus 로고    scopus 로고
    • Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
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    • C.-K. Luk. Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 40-51, June 2001.
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    • Luk, C.-K.1
  • 12
    • 0008602220 scopus 로고
    • PhD thesis, University of Virginia, Department of Computer Science, Apr. Also as TR CS-93-18
    • S. A. Moyer. Access Ordering and Effective Memory Bandwidth. PhD thesis, University of Virginia, Department of Computer Science, Apr. 1993. Also as TR CS-93-18.
    • (1993) Access Ordering and Effective Memory Bandwidth
    • Moyer, S.A.1
  • 16
    • 0028516384 scopus 로고
    • The PowerPC-604 RISC microprocessor
    • Oct.
    • S. P. Song, M. Denman, and J. Chang. The PowerPC-604 RISC microprocessor. IEEE Micro, 14(5):8-17, Oct. 1994.
    • (1994) IEEE Micro , vol.14 , Issue.5 , pp. 8-17
    • Song, S.P.1    Denman, M.2    Chang, J.3
  • 19
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS R10000 superscalar microprocessor: Emphasizing concurrency and latency-hiding techniques to efficiently run large, real-world applications
    • Apr.
    • K. C. Yeager. The MIPS R10000 superscalar microprocessor: Emphasizing concurrency and latency-hiding techniques to efficiently run large, real-world applications. IEEE Micro, 16(2):28-40, Apr. 1996.
    • (1996) IEEE Micro , vol.16 , Issue.2 , pp. 28-40
    • Yeager, K.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.