Equivalent circuit model of on-wafer CMOS interconnects for RFICs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 9, 2005, Pages 1060-1071

  Shi, Xiaomeng ^b   Ma, Jian Guo ^a,c   Yeo, Kiat Seng ^a,b,e   Do, Manh Anh ^a,b,f   Li, Erping ^c,d,g  

^a IEEE

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

^d NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^e Department of Circuits and Systems ^*

^f Institution of Electrical Engineers IEE   (United Kingdom)

^g Institution of Electrical Engineers ^*

Author keywords

Empirical formulas; Lumped equivalent circuit model; Modeling; RF CMOS interconnects; Scalable; Scattering parameters measurement; Skin effect; Substrate losses

Indexed keywords

CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; SCATTERING PARAMETERS; SKIN EFFECT;

EMPIRICAL FORMULA; MODELING; RF CMOS INTERCONNECTS; SCALABLE; SCATTERING PARAMETERS MEASUREMENT; SUBSTRATE LOSSES;

VLSI CIRCUITS;

EID: 27844448067     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.857177     Document Type: Conference Paper

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