Interconnect model at multi-Ghz frequencies incorporating inductance effect

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Volumn , Issue , 2002, Pages 82-86

  Aazadpour, M ^a   Kalkur, T S ^a  

^a University of Colorado at Colorado Springs   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE ANALYSIS; ANALYSIS METHOD; CLOCK TREE; DOMINANT FACTOR; EDA TOOLS; INTERCONNECT DELAY; INTERCONNECT MODELS; SYNCHRONOUS SYSTEM; SYSTEM LEVELS;

INTERCONNECTION NETWORKS;

EID: 27844467355     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. D. Velenis, E. Friedman, M. Ppaefthymiou," A clock Tree Topology Extraction Algorithm For Improving The Tolerance of Clock Distribution Networks to Delay Uncertainly", ISCAS 200/,pp.422-425, 2001.
2. th Annual IEEE Iniernational,pp.9-8/1- 3,1991.