Designing fast on-chip interconnects for deep submicrometer technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 2, 2003, Pages 276-280

  Hossain, Razak ^a   Viglione, Fabrizio ^a   Cavalli, Marco ^b  

^a STMicroelectronics USA   (United States)

^b STMICROELECTRONICS   (Italy)

Author keywords

Capacitive coupling; Critical wire; Deep submicrometer technology; On chip interconnect; Redundant wire; Shielding; Simultaneous redundant switching; Spacing; Wire delay

Indexed keywords

ADDERS; CAPACITANCE; COMPUTER SIMULATION; ENERGY DISSIPATION; INTERCONNECTION NETWORKS; PARALLEL PROCESSING SYSTEMS;

DEEP SUBMICRON (DSM);

CMOS INTEGRATED CIRCUITS;

EID: 0042769408     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.810781     Document Type: Article

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