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Volumn 49, Issue 4-5, 2005, Pages 777-803

Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SYSTEMS; DATA PROCESSING; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; ULSI CIRCUITS;

EID: 25844451118     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.494.0777     Document Type: Review
Times cited : (42)

References (104)
  • 1
    • 0015206785 scopus 로고
    • "On a Pin Versus Block Relationship for Partitions of Logic Graphs"
    • (December)
    • B. S. Landman and R. L. Russo, "On a Pin Versus Block Relationship for Partitions of Logic Graphs," IEEE Trans. Computers C-20, No. 12, 1469-1479 (December 1971).
    • (1971) IEEE Trans. Computers , vol.C-20 , Issue.12 , pp. 1469-1479
    • Landman, B.S.1    Russo, R.L.2
  • 2
    • 0004245602 scopus 로고    scopus 로고
    • "International Technology Roadmap for Semiconductors (ITRS)"
    • 2003 edition, Semiconductor Industry Association (SIA); see
    • "International Technology Roadmap for Semiconductors (ITRS)," 2003 edition, Semiconductor Industry Association (SIA); see http://public.itrs.net/.
  • 3
    • 0019609151 scopus 로고
    • "Electronic Packaging Evolution in IBM"
    • (September)
    • D. P. Seraphim and I. Feinberg, "Electronic Packaging Evolution in IBM," IBM J. Res. & Dev. 25, No. 5, 617-629 (September 1981).
    • (1981) IBM J. Res. & Dev. , vol.25 , Issue.5 , pp. 617-629
    • Seraphim, D.P.1    Feinberg, I.2
  • 5
    • 0032026510 scopus 로고    scopus 로고
    • "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI). I. Derivation and Validation"
    • (March)
    • J. A. Davis, V. K. De, and J. D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI). I. Derivation and Validation," IEEE Trans. Electron Devices 45, No. 3, 580-589 (March 1998).
    • (1998) IEEE Trans. Electron Devices , vol.45 , Issue.3 , pp. 580-589
    • Davis, J.A.1    De, V.K.2    Meindl, J.D.3
  • 6
    • 0032025521 scopus 로고    scopus 로고
    • "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI). II. Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation"
    • (March)
    • J. A. Davis, V. K. De, and J. D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI). II. Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation," IEEE Trans. Electron Devices 45, No. 3, 590-597 (March 1998).
    • (1998) IEEE Trans. Electron Devices , vol.45 , Issue.3 , pp. 590-597
    • Davis, J.A.1    De, V.K.2    Meindl, J.D.3
  • 7
    • 0003604055 scopus 로고    scopus 로고
    • "A Hierarchy of Interconnect Limits and Opportunities for Gigascale Integration (GSI)"
    • Ph.D. thesis, Georgia Institute of Technology
    • J. A. Davis, "A Hierarchy of Interconnect Limits and Opportunities for Gigascale Integration (GSI)," Ph.D. thesis, Georgia Institute of Technology, 1999.
    • (1999)
    • Davis, J.A.1
  • 11
    • 2442640338 scopus 로고    scopus 로고
    • "Prediction of Interconnect Properties for Digital Circuit Design and Exploration"
    • Ph.D. dissertation, University of Ghent, Belgium, July
    • J. Dambre, "Prediction of Interconnect Properties for Digital Circuit Design and Exploration," Ph.D. dissertation, University of Ghent, Belgium, July 2003.
    • (2003)
    • Dambre, J.1
  • 13
    • 12344261796 scopus 로고    scopus 로고
    • "Interpretation of Rent's Rule for Ultralarge-Scale Integrated Circuit Designs, with an Application to Wirelength Distribution Models"
    • (December)
    • M. Y. Lanzerotti, G. Fiorenza, and R. A. Rand, "Interpretation of Rent's Rule for Ultralarge-Scale Integrated Circuit Designs, with an Application to Wirelength Distribution Models," IEEE Trans. Very Large Scale Integration (VLSI) Syst. 12, No. 12, 1330-1347 (December 2004).
    • (2004) IEEE Trans. Very Large Scale Integration (VLSI) Syst. , vol.12 , Issue.12 , pp. 1330-1347
    • Lanzerotti, M.Y.1    Fiorenza, G.2    Rand, R.A.3
  • 14
    • 0018453798 scopus 로고
    • "Placement and Average Interconnection Lengths of Computer Logic"
    • (April)
    • W. E. Donath, "Placement and Average Interconnection Lengths of Computer Logic," IEEE Trans. Circuits & Syst. (CAS) CAS-26, No. 4, 272-277 (April 1979).
    • (1979) IEEE Trans. Circuits & Syst. (CAS) , vol.CAS-26 , Issue.4 , pp. 272-277
    • Donath, W.E.1
  • 15
    • 0019565820 scopus 로고
    • "Wire Length Distribution for Placements of Computer Logic"
    • (May)
    • W. E. Donath, "Wire Length Distribution for Placements of Computer Logic," IBM J. Res. & Dev. 25, No. 2/3, 152-155 (May 1981).
    • (1981) IBM J. Res. & Dev. , vol.25 , Issue.2-3 , pp. 152-155
    • Donath, W.E.1
  • 22
    • 0021481594 scopus 로고
    • "Wirability-Designing Wiring Space for Chips and Chip Packages"
    • (August)
    • W. R. Heller, C. G. Hsi, and W. F. Mikhaill, "Wirability-Designing Wiring Space for Chips and Chip Packages," IEEE Design & Test Magazine 1, 43-51 (August 1984).
    • (1984) IEEE Design & Test Magazine , vol.1 , pp. 43-51
    • Heller, W.R.1    Hsi, C.G.2    Mikhaill, W.F.3
  • 28
    • 0037314645 scopus 로고    scopus 로고
    • "A Priori Wire Length Distribution Models for Multiterminal Nets"
    • (February)
    • D. Stroobandt, "A Priori Wire Length Distribution Models for Multiterminal Nets," IEEE Trans. Very Large Scale Integration (VLSI) Syst. 11, No. 1, 35-43 (February 2003).
    • (2003) IEEE Trans. Very Large Scale Integration (VLSI) Syst. , vol.11 , Issue.1 , pp. 35-43
    • Stroobandt, D.1
  • 30
    • 25844512117 scopus 로고    scopus 로고
    • "Interconnect Planning for Hierarchical FPGAs"
    • Final Report 2002-2003 for MICRO Project 02-046, Collaborating Companies: Xilinx and Mentor Graphics, see
    • M. Marek-Sadowska, "Interconnect Planning for Hierarchical FPGAs," Final Report 2002-2003 for MICRO Project 02-046, Collaborating Companies: Xilinx and Mentor Graphics, 2003; see http://www.ucop.edu/research/micro/02_03/02_046.pdf.
    • (2003)
    • Marek-Sadowska, M.1
  • 32
    • 0037312415 scopus 로고    scopus 로고
    • "Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays"
    • (February)
    • A. Rahman, S. Das, A. P. Chandrakasan, and R. Reif, "Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays," IEEE Trans. Very Large Scale Integration (VLSI) Syst. 11, No. 1, 44-54 (February 2003).
    • (2003) IEEE Trans. Very Large Scale Integration (VLSI) Syst. , vol.11 , Issue.1 , pp. 44-54
    • Rahman, A.1    Das, S.2    Chandrakasan, A.P.3    Reif, R.4
  • 34
    • 6344238664 scopus 로고    scopus 로고
    • "Unifying Mesh- and Tree-Based Programmable Interconnect"
    • (October)
    • A. DeHon, "Unifying Mesh- and Tree-Based Programmable Interconnect," IEEE Trans. Very Large Scale Integration (VLSI) Syst. 12, No. 10, 1051-1065 (October 2004).
    • (2004) IEEE Trans. Very Large Scale Integration (VLSI) Syst. , vol.12 , Issue.10 , pp. 1051-1065
    • DeHon, A.1
  • 38
  • 55
    • 0029207481 scopus 로고
    • "Performance Trends in High-End Processors"
    • (January)
    • G. A. Sai-Halasz, "Performance Trends in High-End Processors," Proc. IEEE 83, No. 1 20-36 (January 1995).
    • (1995) Proc. IEEE , vol.83 , Issue.1 , pp. 20-36
    • Sai-Halasz, G.A.1
  • 56
    • 25844458163 scopus 로고    scopus 로고
    • "Trends in Computer Technology"
    • Technical Report CS-94-17, Department of Computer Systems, Faculty of Mathematics and Computer Science, University of Amsterdam, The Netherlands, November 1994 and October
    • E. H. Dooijes, "Trends in Computer Technology," Technical Report CS-94-17, Department of Computer Systems, Faculty of Mathematics and Computer Science, University of Amsterdam, The Netherlands, November 1994 and October 1999.
    • (1999)
    • Dooijes, E.H.1
  • 57
    • 0034583197 scopus 로고    scopus 로고
    • "Wires, Switches, and Wiring. A Route Toward a Chemically Assembled Electronic Nanocomputer"
    • J. R. Heath, "Wires, Switches, and Wiring. A Route Toward a Chemically Assembled Electronic Nanocomputer," Pure Appl. Chem. 72, No. 1/2, 11-20 (2000); see http://www.iupac.org/publications/pac/2000/ 7201/7201pdf/2_heath.pdf.
    • (2000) Pure Appl. Chem. , vol.72 , Issue.1-2 , pp. 11-20
    • Heath, J.R.1
  • 59
    • 0019527772 scopus 로고
    • "Fundamental Limits in Digital Information Processing"
    • (February)
    • R. W. Keyes, "Fundamental Limits in Digital Information Processing," Proc. IEEE 69, No. 2, 267-278 (February 1981).
    • (1981) Proc. IEEE , vol.69 , Issue.2 , pp. 267-278
    • Keyes, R.W.1
  • 60
    • 0018456357 scopus 로고
    • "The Evolution of Digital Electronics Towards VLSI"
    • (April)
    • R. W. Keyes, "The Evolution of Digital Electronics Towards VLSI," IEEE Trans Electron Devices 26, No. 4, 271-279 (April 1979).
    • (1979) IEEE Trans. Electron Devices , vol.26 , Issue.4 , pp. 271-279
    • Keyes, R.W.1
  • 61
    • 0023539642 scopus 로고
    • "Opportunities for Gigascale Integration"
    • (December)
    • J. D. Meindl, "Opportunities for Gigascale Integration," Solid State Technol. 30, 84-89 (December 1987).
    • (1987) Solid State Technol. , vol.30 , pp. 84-89
    • Meindl, J.D.1
  • 63
    • 0003104503 scopus 로고    scopus 로고
    • "Interconnection Scaling 1 GHz and. Beyond"
    • A. K. Stamper, "Interconnection Scaling 1 GHz and. Beyond," IBM MicroNews 4, No. 2, 1-12 (1998).
    • (1998) IBM MicroNews , vol.4 , Issue.2 , pp. 1-12
    • Stamper, A.K.1
  • 68
    • 0016102199 scopus 로고
    • "Equivalence of Memory to Random Logic"
    • (September); see
    • W. E. Donath, "Equivalence of Memory to Random Logic," IBM J. Res. & Dev. 18, No. 5, 401-407 (September 1974); see http://www. research.ibm.com/journal/rd/185/ibmrd1805D.pdf.
    • (1974) IBM J. Res. & Dev. , vol.18 , Issue.5 , pp. 401-407
    • Donath, W.E.1
  • 69
    • 0032510985 scopus 로고    scopus 로고
    • "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology"
    • (June)
    • J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology," Science 280, 1716-1721 (June 1998).
    • (1998) Science , vol.280 , pp. 1716-1721
    • Heath, J.R.1    Kuekes, P.J.2    Snider, G.S.3    Williams, R.S.4
  • 70
    • 0022061669 scopus 로고
    • "Optimal Interconnection Circuits for VLSI"
    • (May)
    • H. B. Bakoglu and J. D. Meindl, "Optimal Interconnection Circuits for VLSI," IEEE Trans. Electron Devices ED-32, 903-909 (May 1985).
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , pp. 903-909
    • Bakoglu, H.B.1    Meindl, J.D.2
  • 71
    • 3042851200 scopus 로고
    • National Materials Advisory Board, Commission on Engineering and Technical Systems, National Research Council, Washington, DC
    • Materials for High-Density Electronic Packaging and Interconnections, National Materials Advisory Board, Commission on Engineering and Technical Systems, National Research Council, Washington, DC, 1990.
    • (1990) Materials for High-Density Electronic Packaging and Interconnections
  • 72
    • 0020125555 scopus 로고
    • "Lead Reduction Among Combinatorial Logic Circuits"
    • (May); see
    • W. V. Vilkelis, "Lead Reduction Among Combinatorial Logic Circuits," IBM J. Res. & Dev. 26, No. 3, 342-348 (May 1982); see http://www.research.ibm.com/journal/rd/263/ibmrd2603I.pdf.
    • (1982) IBM J. Res. & Dev. , vol.26 , Issue.3 , pp. 342-348
    • Vilkelis, W.V.1
  • 75
    • 0027649412 scopus 로고
    • "Trends and Limits in Monolithic Integration by Increasing the Die Area"
    • (August)
    • C. A. Warwick and A. Ourmazd, "Trends and Limits in Monolithic Integration by Increasing the Die Area," IEEE Trans. Semicond. Mfg. 6, No. 3, 284-289 (August 1993).
    • (1993) IEEE Trans. Semicond. Mfg. , vol.6 , Issue.3 , pp. 284-289
    • Warwick, C.A.1    Ourmazd, A.2
  • 76
    • 0027660725 scopus 로고
    • "Toward Giga-Scale Silicon Integrated Circuits"
    • (September/October)
    • C. A. Warwick, R.-H. Yan, Y. O. Kim, and A. Ourmazd, "Toward Giga-Scale Silicon Integrated Circuits," AT&T Tech. J. 72, No. 5, 50-59 (September/October 1993).
    • (1993) AT&T Tech. J. , vol.72 , Issue.5 , pp. 50-59
    • Warwick, C.A.1    Yan, R.-H.2    Kim, Y.O.3    Ourmazd, A.4
  • 78
    • 0042586557 scopus 로고
    • "Paradigms of Connectivity for Computer Circuits and Networks"
    • H. M. Ozaktas, "Paradigms of Connectivity for Computer Circuits and Networks," Opt. Eng. 31, No. 7, 1563-1567 (1992).
    • (1992) Opt. Eng. , vol.31 , Issue.7 , pp. 1563-1567
    • Ozaktas, H.M.1
  • 79
    • 9644308081 scopus 로고    scopus 로고
    • "Information Flow and Interconnections in Computing: Extensions and Applications of Rent's Rule"
    • H. M. Ozaktas, "Information Flow and Interconnections in Computing: Extensions and Applications of Rent's Rule," J. Parallel & Distr. Computing 64, 1360-1370 (2004).
    • (2004) J. Parallel & Distr. Computing , vol.64 , pp. 1360-1370
    • Ozaktas, H.M.1
  • 82
    • 84975656241 scopus 로고
    • "Free-Space Optical Interconnection Scheme"
    • (May)
    • A. Dickinson and M. E. Prise, "Free-Space Optical Interconnection Scheme," Appl. Opt. 29, No. 14, 2001-2005 (May 1990).
    • (1990) Appl. Opt. , vol.29 , Issue.14 , pp. 2001-2005
    • Dickinson, A.1    Prise, M.E.2
  • 83
    • 25844488962 scopus 로고    scopus 로고
    • Stanford University System Performance Simulator (SUSPENS); see
    • Stanford University System Performance Simulator (SUSPENS); see http://public.itrs.net/Files/2001ITRS/Links/design/GTX/PER_STUDY_DOCS/ GTX_SUSPENS_doc.html.
  • 84
    • 0029250448 scopus 로고
    • "A Framework for Insight into the Impact of Interconnect on 0.35-μm VLSI Performance"
    • (February); see
    • P. Raje, "A Framework for Insight into the Impact of Interconnect on 0.35-μm VLSI Performance," Hewlett-Packard J. Online 46, No. 1 (February 1995); see http://www.hpl.hp.com/hpjournal/95fab/feb95a15.htm.
    • (1995) Hewlett-Packard J. Online , vol.46 , Issue.1
    • Raje, P.1
  • 86
    • 25844476810 scopus 로고    scopus 로고
    • Rensselaer Interconnect Performance Estimator (RIPE); see
    • Rensselaer Interconnect Performance Estimator (RIPE); see http://public. itrs.net/Files/2001ITRS/Links/design/GTX/RULES/ripe40-1.pdf.
  • 87
    • 0000712307 scopus 로고    scopus 로고
    • "System-Level Performance Modeling with BACPAC-Berkeley Advanced Chip Performance Calculator"
    • D. Sylvester and K. Keutzer, "System-Level Performance Modeling with BACPAC-Berkeley Advanced Chip Performance Calculator," Proceedings of System-Level Interconnect Prediction (SLIP), 1999, pp. 109-114; see http://www.eecs.umich.edu/~dennis/bacpac/.
    • (1999) Proceedings of System-Level Interconnect Prediction (SLIP) , pp. 109-114
    • Sylvester, D.1    Keutzer, K.2
  • 89
    • 25844489847 scopus 로고    scopus 로고
    • "GSRC Technology Extrapolation (GTX)"
    • The GTX Framework, see
    • The GTX Framework, "GSRC Technology Extrapolation (GTX)"; see http://vlsicad.ucsd.edu/GSRC/GTX/.
  • 90
    • 25844449056 scopus 로고    scopus 로고
    • IBM Corporate Archives: 1401 Data Processing System; see
    • IBM Corporate Archives: 1401 Data Processing System; see http://www-03. ibm.com/ibm/history/exhibits/mainframe/mainframe_PP1401.html.
  • 91
    • 25844498129 scopus 로고    scopus 로고
    • "The 1401"
    • F. da Cruz, "The 1401"; see http://www.columbia.edu/acis/ history/1401.html.
    • da Cruz, F.1
  • 92
    • 25844469859 scopus 로고    scopus 로고
    • IBM Corporate Archives: 1410 Data Processing System; see
    • IBM Corporate Archives: 1410 Data Processing System; see http://www-03. ibm.com/ibm/history/exhibits/mainframe/mainframe_PP1410.html.
  • 93
    • 25844479720 scopus 로고    scopus 로고
    • "The 1410"
    • see
    • F. da Cruz, "The 1410"; see http://www.columbia.edu/acis/ history/1410.html.
    • da Cruz, F.1
  • 94
    • 0003593511 scopus 로고
    • The MIT Press, Cambridge, MA, pp. 167-177, 234-236, 265-276, 285-288
    • E. W. Pugh, Building IBM: Shaping an Industry and Its Technology, The MIT Press, Cambridge, MA, 1995, pp. 167-177, 234-236, 265-276, 285-288, and 301-305.
    • (1995) Building IBM: Shaping an Industry and Its Technology , pp. 301-305
    • Pugh, E.W.1
  • 96
    • 4043058148 scopus 로고    scopus 로고
    • "The IBM eServer z990 Microprocessor"
    • (May/July)
    • T. J. Slegel, E. Pfeffer, and J. A. Magee, "The IBM eServer z990 Microprocessor," IBM J. Res. & Dev. 48, No. 3/4, 295-309 (May/ July 2004).
    • (2004) IBM J. Res. & Dev. , vol.48 , Issue.3-4 , pp. 295-309
    • Slegel, T.J.1    Pfeffer, E.2    Magee, J.A.3
  • 97
    • 12344257052 scopus 로고    scopus 로고
    • "IBM Raises Curtain on POWER5"
    • Archive 10, (October)
    • P. N. Glaskowsky, "IBM Raises Curtain on POWER5," Microproc. Rep. 17, Archive 10, 13-14 (October 2003).
    • (2003) Microproc. Rep. , vol.17 , pp. 13-14
    • Glaskowsky, P.N.1
  • 99
    • 0037230305 scopus 로고    scopus 로고
    • "Estimating the Efficiency of Collaborative Problem-Solving, with Applications to Chip Design"
    • (January); see
    • M. Y. L. Wisniewski, E. Yashchin, R. L. Franch, D. P. Conrady, G. Fiorenza, and I. C. Noyan, "Estimating the Efficiency of Collaborative Problem-Solving, with Applications to Chip Design," IBM J. Res. & Dev. 47, No. 1, 77-88 (January 2003); see http://www. research.ibm.com/journal/rd/471/wisniewski.pdf.
    • (2003) IBM J. Res. & Dev. , vol.47 , Issue.1 , pp. 77-88
    • Wisniewski, M.Y.L.1    Yashchin, E.2    Franch, R.L.3    Conrady, D.P.4    Fiorenza, G.5    Noyan, I.C.6
  • 102
    • 0035853071 scopus 로고    scopus 로고
    • "The Increasingly Plastic, Hormone-Responsive Adult Brain"
    • S. M. Breedlove and C. L. Jordan, "The Increasingly Plastic, Hormone-Responsive Adult Brain," Proc. Natl. Acad. Sci. 98, No. 6, 2956-2957 (2001).
    • (2001) Proc. Natl. Acad. Sci. , vol.98 , Issue.6 , pp. 2956-2957
    • Breedlove, S.M.1    Jordan, C.L.2
  • 103
    • 0029398463 scopus 로고
    • "The Connectivity of the Brain: Multi-Level Quantitative Analysis"
    • J. M. J. Murre and D. P. F. Sturdy, "The Connectivity of the Brain: Multi-Level Quantitative Analysis," Biol. Cybern. 73, 529-545 (1995).
    • (1995) Biol. Cybern. , vol.73 , pp. 529-545
    • Murre, J.M.J.1    Sturdy, D.P.F.2
  • 104
    • 25844438686 scopus 로고    scopus 로고
    • "The Basic Wiring Diagram of the Brain"
    • B. James, "The Basic Wiring Diagram of the Brain," Kybernetes 27, No. 1, 88-89 (1998).
    • (1998) Kybernetes , vol.27 , Issue.1 , pp. 88-89
    • James, B.1


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