Testing and defect tolerance: A rent's rule based analysis and implications on nanoelectronics

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2004, Pages 280-288

  Kumar, Arvind ^a   Tiwari, Sandip ^a  

^a Cornell University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING ARCHITECTURES; DEFECT DENSITY; DEFECT TOLERANCE; SYSTEM PERFORMANCE;

COMPUTER SOFTWARE; COSTS; PARAMETER ESTIMATION; VLSI CIRCUITS;

NANOTECHNOLOGY;

EID: 24944448843     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347850     Document Type: Conference Paper

References (11)

1. H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.
2. J. Davis, V. De, and J. Meindl. A stochastic wire-length distribution for gigascale integration - part 1: Derivation and validation. IEEE Trans. on Electron Devices, 45(3):580-589, 1998.
3. J. Davis, V. De, and J. Meindl. A stochastic wire-length distribution for gigascale intergration - part 2: Applications to clock frequency, power dissipation, and chip size estimation. IEEE Trans. on Electron Devices, 45(3):590-597, 1998.
4. W. E. Donath. On the equivalence of memory to random logic. IBM J. of Res. and Develop., 18:401-407, 1974.
5. W. E. Donath. Placement and average interconnection lengths of computer logic. IEEE Trans. on Circuit and Systems, CAS-26:272-277, 1979.
6. M. Feuer. Connectivity of random logic. IEEE Trans. on Computers, C-31:29-33, 1982.
7. J. R. Heath, P. J. Kuekes, G. S. Snider, and S. Williams. A defect-tolerant computer architecture: Opportunities for nanotechnology. Science, 280:1716-1721, 1998.
8. W. Heller, C. Hsi, and W. Mikhail. Wirability - designing wiring space for chips and chip packages. IEEE Design and Test Mag., pages 43-51, 1984.
9. A. Kumar and S. Tiwari. Defect tolerance for nanocomputer architecture. In Proc. of Intl Workshop on System Level Interconnect Prediction (SLIP), 2004.
10. D. Stroobandt. A Priori Wire Length Estimates for Digital Design. Kluwer Publications, 2001.
11. X. Yang, R. Kastnr, and M. Sarrafzadeh. Congestion during top-down placement. IEEE Trans. on CAD of ICs and Systems, 21(1):72-80, 2002.