Global interconnect design in a three-dimensional system-on-a-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 4, 2004, Pages 367-372

  Joyner, James W ^a   Zarkesh Ha, Payman ^b   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

Global wiring; Integrated circuit interconnection; Net length; System level interconnect prediction; System on a chip (SoC); Three dimensional (3 D) integration; Wirelength distribution

Indexed keywords

GLOBAL WIRING; INTEGRATED CIRCUIT INTERCONNECTION; NET LENGTH; SYSTEM LEVEL INTERCONNECT PREDICTION; SYSTEM ON A CHIP (SOC); THREE DIMENSIONAL INTEGRATION; WIRELENGTH DISTRIBUTION;

ASPECT RATIO; BONDING; COMPUTER SIMULATION; ELECTRIC WIRING; MATHEMATICAL MODELS; PRODUCT DESIGN; RANDOM PROCESSES; SILICON WAFERS;

MICROPROCESSOR CHIPS;

EID: 2442718053     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.825835     Document Type: Conference Paper

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