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Volumn 98, Issue 2, 2005, Pages

Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction

Author keywords

[No Author keywords available]

Indexed keywords

EQUIVALENT OXIDE THICKNESS (EOT); GATE ELECTRIC THICKNESS; METAL-INSULATOR-SEMICONDUCTOR (MIS); SILICA LAYERS;

EID: 23844503318     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1988967     Document Type: Article
Times cited : (85)

References (32)
  • 23
    • 33645200863 scopus 로고    scopus 로고
    • Ph.D. thesis, North Carolina State University
    • S. Han, Ph.D. thesis, North Carolina State University, 2003.
    • (2003)
    • Han, S.1
  • 24
    • 33645190597 scopus 로고    scopus 로고
    • J. Hauser, CVC program V5.0, NCSU Software, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, 2000; see also J. R. Hauser and K. Ahmed, Characterization and Metrology for ULSI Technology, AIP Conf. Proc. No. 449 (AIP, Woodbury, NY, 1998), p. 235.
    • Hauser, J.1
  • 25
    • 0001954222 scopus 로고    scopus 로고
    • AIP Conf. Proc. No. AIP, Woodbury, NY
    • J. Hauser, CVC program V5.0, NCSU Software, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, 2000; see also J. R. Hauser and K. Ahmed, Characterization and Metrology for ULSI Technology, AIP Conf. Proc. No. 449 (AIP, Woodbury, NY, 1998), p. 235.
    • (1998) Characterization and Metrology for ULSI Technology , Issue.449 , pp. 235
    • Hauser, J.R.1    Ahmed, K.2
  • 32
    • 33645201204 scopus 로고    scopus 로고
    • N. Inoue (private communication).
    • Inoue, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.