NoCGEN: A template based reuse methodology for networks on chip architecture

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 717-720

  Chan, Jeremy ^a   Parameswaran, Sri ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; GRAPHIC METHODS; MATHEMATICAL MODELS; PROBLEM SOLVING; RANDOM PROCESSES; SWITCHING; TOPOLOGY;

CHIP ARCHITECTURE; ROUTING ALGORITHMS; SYSTEMS ON CHIPS (SOC);

MICROPROCESSOR CHIPS;

EID: 2342632456     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. ARM. Amba 2.0 specification, 2002.
2. A. Chien. A cost and speed model for k-ary n-cube wormhole routers. In Hot Interconnects, Stanford, 1993.
3. W. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In DAC, pages 684-689, 2001.
4. J. Duato, S. Yalamanchili, and L. Ni. Interconnection Networks: An engineering approach. Morgan Kaufmann, 2003.
5. P. Guerrier and A. Greiner. A generic architecture for on-chip packet-switched interconnections. In DATE, pages 250-256, 2000.
6. R. Ho, K. Mai, and M. A. Horowitz. The future of wires. Proceedings of the IEEE, 89(4):490-504, 2001.
7. J. Hu and R. Marculescu. Energy-aware mapping for tile-based noc architectures under performance constraints. In ASPDAC, 2003.
8. M. Keating. Reuse Methedology Manual. Kluwer Academic Publishers, 1998.
9. S. Kumar, A. Jantsch, J.-P. Solninen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani. A network on chip architecture and design methodology. In ISVLSI, 2002.
10. K. Lahiri, A. Raghunathan, and S. Dey. Fast performance analysis of bus-based system-on-chip communication architectures. Computer-Aided Design, pages 566-572, 1999.
11. K. Lahiri, A. Raghunathan, and G. Lakshminarayana. Lotterybus: A new high-performance communication architecture for system-on-chip designs. In DAC, Las Vegas, 2001.
12. J. Liang, S. Swaminathan, and R. Tessier. Asoc: a scalable, single-chip communications architecture. In Parallel Architectures and Compilation Techniques, 2000.
13. N. McKeown. The islip scheduling algorithm for input-queued switches. IEEE/ACM Transactions on Networking, pages 188-201, 1999.
14. P. G. Paulin, C. Pilkington, and E. Bensoudane. Stepnp: A system-level exploration platform for network processors. IEEE Design and Test of Computers, pages 17-26, 2002.
15. L.-S. Peh. Flow Control and Micro-Architectural Mechanisms for Extending the Performance of Interconnection Networks. Phd, Stanford University, 2001.
16. E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In DATE, 2003.
17. A. Sangiovannl-Vincentelli and G. Martin. Platform-based design and software design methodology for embedded systems. IEEE Design and Test of Computers, pages 23-33, November 2001 2001.
18. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, R. Jan, and A. Sangiovanni-Vincentelli. Addressing the system-on-a-chip interconnect woes through communication-based design. In DAC, 2001.
19. D. Siguenza Tortosa and J. Nurmi. Vhdl-based simulation environment for proteo noc. In HLDVT02, Cannes, France, 2001.
20. P. Wielage and K. Goossens. Networks on silicon: blessing or nightmare? In Euromicro Symposium on Digital System Design, pages 196-200, 2002.
21. D. Wingard. Micronetwork-based integration for socs. In DAC, Las Vegas, 2001.