Fast performance analysis of bus-based system-on-chip communication architectures

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 566-572

  Lahiri, Kanishka ^a   Raghunathan, Anand ^a   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTER SIMULATION; GRAPH THEORY; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PERFORMANCE; USER INTERFACES;

BUS AND SYNCHRONIZATION EVENT GRAPH; BUS BASED SYSTEM ON CHIP COMMUNICATION ARCHITECTURE; SYSTEM LEVEL PERFORMANCE ANALYSIS TECHNIQUE;

LOGIC DESIGN;

EID: 0033319378     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)