Investigation of strained Si/SiGe devices by MC simulation

Solid-State Electronics

Volumn 48, Issue 8, 2004, Pages 1417-1422

  Jungemann, C ^a   Subba, N ^b   Goo, J S ^b   Riccobene, C ^b   Xiang, Q ^b   Meinerzhagen, B ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Monte Carlo simulation; MOSFET; SiGe; Strained Si

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MATHEMATICAL MODELS; MONTE CARLO METHODS; PHONONS; POISSON EQUATION; SEMICONDUCTOR DOPING; SILICON; STRAIN; THRESHOLD VOLTAGE;

BANDGAP ENGINEERING; SIGE; STRAINED SI;

MOSFET DEVICES;

EID: 2342588748     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.02.016     Document Type: Article

References (36)

1. Iyer S.S., Patton G.L., Stork J.M.C., Meyerson B.S., Harame D.L. Heterojunction bipolar transistors using Si-Ge alloys. IEEE Trans. Electron Devices. 36(10):1989;2043-2064.
2. Ismail K., Meyerson B.S., Rishton S., Chu J., Nelson S., Nocera J. High-transconductance n-type Si/SiGe modulation-doped field-effect transistors. IEEE Electron Device Lett. 13(5):1992;229-231.
3. Welser J., Hoyt J.L., Takagi S., Gibbons J.F. Strain dependence of the Performance Enhancement in Strained-Si n-MOSFETs. IEDM Tech. Dig. 1994;373-376.
4. Hoyt J.L., Nayfeh H.M., Eguchi S., Aberg I., Xia G., Drake T., et al. Strained silicon MOSFET technology. IEDM Tech. Dig. 2002;23-26.
5. Rim K, Koester S, Hargrove M, Chu J, Mooney PM, Ott J, et al. Strained Si NMOSFETs for high performance CMOS technology. In: Symposium on VLSI Technology Digest of Technical Papers. 2001. p. 59-60.
6. 2 SRAM cell. IEDM Tech. Dig. 2002;61-64.
7. Ota K., Sugihara K., Sayama H., Uchida T., Oda H., Emori T., et al. Novel locally strained channel technique for high performance 55 nm CMOS. IEDM Tech. Dig. 2002;27-30.
8. x grown on 〈0. 0 1〉 silicon substrate IEEE Trans. Electron Devices. 39(9):1992;2082-2089.
9. Fischetti M.V., Laux S.E. Band structure, deformation potentials, and carrier mobility in strained Si, Ge and SiGe alloys. J. Appl. Phys. 80:1996;2234-2252.
10. Bufler F., Fichtner W. Scaling of Strained-Si n-MOSFETs into the ballistic regime and associated anisotropic effects. IEEE Trans. Electron Devices. 50(2):2003;278-284.
11. Bude J, MOSFET modeling into the ballistic regime. In: Proc. SISPAD, 2000. p. 23-6.
12. Goo J.-S., Xiang Q., Takamura Y., Wang H., Arasnia F., Paton E.N., et al. Scalability of strained-Si nMOSFETs down to 25 nm gate length. IEEE Electron Device Lett. 24(5):2003;351-353.
13. Goo J.-S., Xiang Q., Takamura Y., Arasnia F., Paton E., Besser P., et al. Band offset induced threshold variation in strained-Si nMOSFETs. IEEE Electron Device Lett. 24(9):2003;568-570.
14. Rim K., Anderson R., Boyd D., Cardone F., Chan K., Chen H., et al. Strained Si CMOS (SS CMOS) technology: Opportunities and challenges. Solid-State Electron. 47:2003;1133-1139.
15. Rim K., Narashima S., Longstreet M., Mocuta A., Cai J. Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs. IEDM Tech. Dig. 2002;43-46.
16. Jacoboni C., Lugli P. The Monte Carlo method for semiconductor device simulation. 1989;Springer, Wien.
17. y substrates. Phys. Rev. B. 48:1993;14276-14287.
18. Jungemann C., Meinerzhagen B. Hierarchical device simulation, computational microelectronics. 2003;Springer, New York, Wien.
19. Fischetti M., Gámiz F., Hänsch W. On the enhanced electron mobility in strained-silicon inversion layers. J. Appl. Phys. 92(12):2002;7320-7324.
20. Fuchs K., Wills H.H. The conductivity of thin metallic films according to the electron theory of metals. Proc. Camb. Philos. Soc. 34:1938;100-108.
21. Sangiorgi E., Pinto M.R. A semi-empirical model of surface scattering for Monte Carlo simulation of silicon n-MOSFET's. IEEE Trans. Electron Devices. 39(2):1992;356-361.
22. Hockney R., Eastwood J. Computer simulation using particles. 1988;Institute of Physics Publishing, Bristol, Philadelphia.
23. x substrates. Appl. Phys. Lett. 63:1993;186-188.
24. Takagi S., Toriumi A., Iwase M., Tango H. On the universality of inversion layer mobility in Si MOSFET's: Part I - Effects of substrate impurity concentration. IEEE Trans. Electron Devices. 41:1994;2357-2362.
25. Nayfeh H.M., Hoyt J.L., Leitz C.W., Pitera A.J., Fitzgerald E.A., Antoniadis D.A. Electron inversion layer mobility in strained-si n-MOSFETs with high channel doping concentration achieved by ion implantation. DRC. 60:2002;43-44.
26. 2 interface as determined by a time-of-flight technique. J. Appl. Phys. 54:1983;1445-1456.
27. Jungemann C., Emunds A., Engl W.L. Simulation of linear and nonlinear electron transport in homogeneous silicon inversion layers. Solid-State Electron. 36:1993;1529-1540.
28. Lundstrom M., Ren Z. Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans. Electron Devices. 49(1):2002;133-141.
29. Lochtefeld A., Antoniadis D. Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress. IEEE Electron Device Lett. 22(12):2001;591-593.
30. Jungemann C., Meinerzhagen B. On the applicability of nonself-consistent Monte Carlo device simulations. IEEE Trans. Electron Devices. 49(6):2002;1072-1074.
31. Keith S, Bufler FM, Meinerzhagen B. Full band Monte-Carlo device simulation of an 0.1 μm n-channel MOSFET in strained silicon material. In: Proc. ESSDERC, Stuttgart, 1997. p. 200-3.
32. 2 interface of a MOSFET. Solid-State Electron. 32:1989;839-849.
33. Price P.J. Monte Carlo calculation of electron transport in solids. Semiconductors and Semimetals. 14:1979;249-309.
34. Lifshitz E.M., Pitaevskii L.P. Physical kinetics. Vol. 10 of courses of theoretical physics. 1981;Butterworth-Heinemann, Oxford, UK.
35. Lundstrom M. Elementary scattering theory of the Si MOSFET. IEEE Electron Device Lett. 18(7):1997;361-363.
36. Takagi S-I. Re-examination of subband structure engineering in ultra-short channel MOSFETs under ballistic carrier transport. In: Digest of Technical Papers, Symposium on VLSI Technology, 2003. p. 115-116.