Technological challenges of advanced CMOS processing and their impact on design aspects

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 275-282

  Claeys, Cor ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC SWITCHES; ELECTROPLATING; GATES (TRANSISTOR); LITHOGRAPHY; NANOTECHNOLOGY; RESEARCH AND DEVELOPMENT MANAGEMENT; SCHEDULING;

ELECTRON PROJECTION LITHOGRAPHY (EPL); GATE STACKS; NEXT GENERATION LITHOGRAPHY (NGL); TECHNOLOGICAL INNOVATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 2342473839     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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