High quality ultra-thin (1.5 nm) TiO2/Si3N4 gate dielectric for deep sub-micron CMOS technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 137-140

  Guo, Xin ^a   Wang, Xiewen ^a   Luo, Zhijiong ^a   Ma, T P ^a   Tamagawa, T ^a  

^a YALE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TRAPS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOSFET DEVICES; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON NITRIDE; THERMODYNAMIC STABILITY; TITANIUM DIOXIDE; ULTRATHIN FILMS; VAPOR DEPOSITION; X RAY DIFFRACTION ANALYSIS;

CAPACITANCE VOLTAGE CHARACTERISTICS; DEEP SUBMICRON CMOS TECHNOLOGY; EQUIVALENT OXIDE THICKNESS; GATE DIELECTRICS; JET VAPOR DEPOSITION; POST DEPOSITION ANNEAL; TRAP DENSITY;

DIELECTRIC MATERIALS;

EID: 0033325113     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)