An AES crypto chip using a high-speed parallel pipelined architecture

Microprocessors and Microsystems

Volumn 29, Issue 7, 2005, Pages 317-326

  Yoo, S M ^a   Kotturi, D ^b   Pan, D W ^a   Blizzard, J ^b  

^a UNIVERSITY OF ALABAMA IN HUNTSVILLE   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Encryption algorithm; Hardware implementation; Parallel pipelined design; Throughput

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER NETWORKS; COMPUTER SOFTWARE; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; SECURITY OF DATA; THROUGHPUT;

DATA ENCRYPTION STANDARD (DES); ENCRYPTION ALGORITHMS; HARDWRE IMPLEMENTATION; PARALLEL PIPELINED DESIGN;

MICROPROCESSOR CHIPS;

EID: 22644433955     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2004.12.001     Document Type: Article

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