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Volumn 41, Issue 12, 2003, Pages 86-91

A High-Throughput Low-Cost AES Processor

Author keywords

[No Author keywords available]

Indexed keywords

ELLIPTIC CURVE ALGORITHMS; LOOKUP TABLE (LUT);

EID: 0348013287     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCOM.2003.1252803     Document Type: Article
Times cited : (76)

References (15)
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    • K. U. Jarvinen, M. T. Tommiska, and J. O. Skytta, "A Fully Pipelined Memoryless 17.8 Gb/s AES-128 Encryptor," Proc. Int'l. Symp. FPGA, Monterey, CA, 2003, pp. 207-15.
    • (2003) Proc. Int'l. Symp. FPGA , pp. 207-215
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  • 5
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    • I. Verbauwhede, P. Schaumont, and H. Kuo, "Design and Performance Testing of a 2.29-GB/s Rijndael Processor," IEEE J. Solid-State Circuits, vol. 38, no. 3, Mar. 2003, pp. 569-72.
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  • 6
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    • Two Methods of Rijndael Implementation in Reconfigurable Hardware
    • May, LNCS, Springer-Verlag
    • V. Fischer and M. Drutarovsky, "Two Methods of Rijndael Implementation in Reconfigurable Hardware," Cryptographic Hardware and Embedded Sys. 2001, May 2001, vol. 2162 of LNCS, Springer-Verlag, pp. 77-92.
    • (2001) Cryptographic Hardware and Embedded Sys. 2001 , vol.2162 , pp. 77-92
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  • 7
    • 0036398166 scopus 로고    scopus 로고
    • A 10Gb/s full-AES Crypto Design with a Twisted-BDD S-Box Architecture
    • Freiburg, Germany, Sept.
    • S. Morioka and A. Satoh, "A 10Gb/s full-AES Crypto Design with a Twisted-BDD S-Box Architecture," Proc. IEEE Int'l. Conf. Comp. Des., Freiburg, Germany, Sept. 2002, pp. 98-103.
    • (2002) Proc. IEEE Int'l. Conf. Comp. Des. , pp. 98-103
    • Morioka, S.1    Satoh, A.2
  • 9
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    • A. Satoh et al., "A Compact Rijndael HARDWARE Architecture with S-Box Optimization," ASIACRYPT 2001, 2001. LNCS, vol. 2248, pp. 239-54.
    • (2001) ASIACRYPT 2001 , vol.2248 , pp. 239-254
    • Satoh, A.1
  • 10
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    • An ASIC Implementation of the AES SBoxes
    • LNCS, Springer-Verlag
    • J. Wolkerstorfer, E. Oswald, and M. Lamberger, "An ASIC Implementation of the AES SBoxes," CT-RSA 2002. 2002. vol. 2271 of LNCS, Springer-Verlag, pp. 67-78.
    • (2002) CT-RSA 2002 , vol.2271 , pp. 67-78
    • Wolkerstorfer, J.1    Oswald, E.2    Lamberger, M.3
  • 11
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    • A High-throughput Low-cost AES Cipher Chip
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.