A hardware implementation in FPGA of the Rijndael algorithm

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Chiţu, Cristian ^a,b   Chien, David ^b   Chien, Charles ^b   Verbauwhede, Ingrid ^a,b   Chang, Frank ^a,b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b G Plus Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CRYPTOGRAPHY; FREQUENCIES; HARDWARE;

RIJNDAEL ALGORITHMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036974109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. H. Kuo, I. Verbauwhede, "Architectural Optimization for a 1.82 Gb/s VLSI Implementation of the AES Rijndael algorithm", Cryptographic Hardware and Embedded Systems (CHES 2001), LNCS 2162, pp. 51-64, Springer-Verlag.
2. P. Schaumont, H. Kuo, I. Verbauwhede, "Unlocking the Design Secrets of a 2.29 Gb/s Rijndael Core", Design Automation Conference 2002.
3. National Institute of Standards and Technology, "Advanced Encryption Standard (AES)", http://csrc.nist.gov/publications/fips, FIPS 197, November 2001.
4. Vincent Rijmen, "The block cipher Rijndael", http://www.esat.kuleuven.ac.be/̃rijmen/rijndael.
5. Xilinx, "ISE 4 User Guide", Xilinx, Inc., 2001.
6. Insight Electronics, "Virtex II Development Kit", http://www.insight-electronics.com/virtexII, Memec Inc., San Diego, CA 92121.
7. Agilent Technologies, "Training Kit for the Agilent Technologies 16700 - Series Logic Analysis System, Making Basic Measurements", 16700-97020, Agilent Technologies, August 2001.
8. Kris Gaj and Pawel Chodowiec, "Fast implementation and fair comparison of the final candidates for Advanced Encryption Standard using Field Programmable Gate Arrays", Proceedings RSA Security Conference, San Francisco, CA, April 8-12, 2001.