A low device occupation IP to implement Rijndael algorithm

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 20-25

  Panato, Alex ^a   Barcelos, Marcelo ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED ENCRYPTION STANDARD; BIT SIZE; CLOCK FREQUENCY; KEY SIZES; LOW AREA; NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY; RIJNDAEL ALGORITHM; SYMMETRIC CIPHER;

CRYPTOGRAPHY; DATA PRIVACY; EXHIBITIONS;

ALGORITHMS;

EID: 2342620388     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253799     Document Type: Conference Paper

References (16)

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12. DAEMEN, Joan e RIJMEN, Pawel. The block cipher Rijndael. Rijndael official homepage, available at http://www.esat.kuleuven.ac.be/~rijmen/rijndael/
13. MROCZKOWSKI, Piotr. Implementation of the block cipher Rijndael using Altera FPGA. PDF file available at http://csrc.nist.gov/encryption/aes/round2/ comments/200 00510-pmroczkowski.pdf (Aug. 2001
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16. PANATO, Alex; NEUBERGER, Gustavo; LIMA, Fernanda; LAZZARI, Cristiano; REIS, Ricardo. Testing a Rijndael VHDL Description to Single Event Upsets. SIM 2002, Canela, Brazil, 28 and 29 June 2002. PDF file available at www.inf.ufrgs.br/~panato/sim02.pdf