An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 4, 2001, Pages 545-557

  Elbirt, A J ^a   Yip, W ^a   Chetwynd, B ^a   Paar, C ^a  

^a Worcester Polytechnic Institute   (United States)

Author keywords

Algorithm agility; Block cipher; Cryptography; Field programmable gate array (FPGA); VHDL

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS; MULTIPROGRAMMING; OPTIMIZATION;

ALGORITHM AGILITY; ENCRYPTION ALGORITHMS;

CRYPTOGRAPHY;

EID: 0035425820     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.931230     Document Type: Article

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