An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 292-302

  Saggese, G P ^a   Mazzeo, A ^a   Mazzocca, N ^b   Strollo, A G M ^a  

^a UNIVERSITY OF NAPLES FEDERICO II   (Italy)

^b SECOND UNIVERSITY OF NAPLES   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA PRIVACY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN;

ADVANCED ENCRYPTION STANDARD; BETTER PERFORMANCE; DESIGN TECHNIQUE; EFFICIENT IMPLEMENTATION; FPGA IMPLEMENTATIONS; NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY; PERFORMANCE ANALYSIS; RIJNDAEL ALGORITHM;

CRYPTOGRAPHY;

EID: 35248824196     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_29     Document Type: Article

References (10)

1. J. Daemen and V. Rijmen, "AES Proposal: Rijndael, AES Algorithm Submission", September 1999, available at http://www.nist.gov/CryptoToolkit
2. National Institute of Standards and Technology (NIST), FIPS Publication 197, "Advanced Encryption Standard (AES)", November 2001.
3. A. Menezes, P. van Oorschot, and S. Vanstone, "Handbook of Applied Cryptography", CRC Press, 1996.
4. National Institute of Standards and Technology (NIST), Special Publication 800-38A, "Recommendation for Block Cipher Modes of Operation", December 2001.
5. ∼mveaver/sfra/rijndael.pdf
6. C. Leiserson, F. Rose, and J. Saxe, "Optimizing synchronous circuitry by retiming", Third Caltech Conference On VLSI, March 1993.
7. A. Labbé, A. Pérez, "AES Implementations on FPGA: Time-Flexibility Tradeoff", Proceedings of FPL02, pp. 836-844.
8. P.R. Schaumont, H. Kuo, and I.M. Verbauwhede, "Unlocking the Design Secrets of a 2.29 Gb/s Rijndael Processor", Proceedings of the International Design Automation Conference 2002 (DAC02), pp. 634-639.
9. A.J. Elbirt, W. Yip, B. Chetwynd, and C. Paar, "An FPGA-Based Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists", IEEE Trans. on VLSI Systems, Vol.9, No.4, August 2001, pp. 545-557.
10. Amphion Semiconductor, "CS5210-40: High Performance AES Encryption Cores", Amphion(TM), Febrauary 2003, available at http://www.amphion.com/ cs5210.html