A 21.54 Gbits/s fully pipelined AES processor on FPGA

Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Volumn , Issue , 2004, Pages 308-309

  Hodjat, Alireza ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMATIC; SHIFT ROWS; XORING;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CALCULATIONS; CRYPTOGRAPHY; DATA REDUCTION; PROGRAM PROCESSORS; SCHEDULING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 18644367181     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2004.1     Document Type: Conference Paper

References (13)

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5. I. Verbauwhede, P. Schaumont, H. Kuo, "Design and Performance testing of a 2.29 Gb/s Rijndael Processor", IEEE Journal of Solid-State Circuits (JSSC), March 2003.
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10. Standaert et al, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs", CHES 2003, LNCS 2779, pp. 334-350, 2003.
11. Saggese et al, "An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm", FPL 2003, LNCS 2778, pp. 292-302, 2003.
12. V. Rijmen, "Efficient Implemenation of the Rijndael S-box", available at: http://esat.kuleuven.ac.be/~rijmen/rijndael/sbox.pdf
13. Jarvinen et al, "A fully pipelined memoryless 17.8 Gbps AES-128 encryptor", International Symposium on Field Programmable Gate Arrays, pp. 207-215, 2003.