Unlocking the design secrets of a 2.29 GB/s Rijndael processor

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 634-639

  Schaumont, Patrick R ^a   Kuo, Henry ^a   Verbauwhede, Ingrid M ^a  

^a University of California   (United States)

Author keywords

Domain specific; Encryption; Low power; Rijndael

Indexed keywords

ENCRYPTION CHIPS;

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CRYPTOGRAPHY;

MICROPROCESSOR CHIPS;

EID: 0036052456     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012702     Document Type: Article

References (13)

1. The block cipher Rijndael, smart card research and applications
2. Architectural optimization for a 1.82 Gb/s VLSI implementation of the AES Rijndael algorithm, cryptographic hardware and embedded systems (CHES 2001)
3. Security at the interact layer
4. AES Key agility issues in high speed IPsec implementations
5. High performance single chip FPGA Rijndael algorithm implementations
6. Two methods of Rijndael implementations in recunfigurable hardware
7. Experimental testing of the gigabit IPSec-compliant implementations of Rijndael and triple DES using SLAAC-1V FPGA accelerator board
8. Hardware evaluation of the AES finalists
9. A compact Rijndael hardware architecture with S-box optimization