A highly regular and scalable AES hardware architecture

IEEE Transactions on Computers

Volumn 52, Issue 4, 2003, Pages 483-491

  Mangard, Stefan ^a   Aigner, Manfred ^a   Dominikus, Sandra ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Advanced encryption standard (AES); Hardware architecture; IP module; Regularity; Scalability; VLSI

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; INTERNET; NETWORK PROTOCOLS; PERFORMANCE; VLSI CIRCUITS;

ADVANCED ENCRYPTION STANDARD; INTERNET PROTOCOL MODULE; SCALABILITY;

CRYPTOGRAPHY;

EID: 0038300424     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1190589     Document Type: Article

References (18)

1. J. Daemen and V. Rijmen, The Design of Rijndael. Springer-Verlag, 2002.
2. Nat'l Inst. of Standards and Technology, "Federal Information Processing Standard 197, The Advanced Encryption Standard (AES)," http:;//csrc.nist.gov/publications/fips/fisp197/fips-197.pdf, 2001.
3. Nat'l Inst. of Standards and Technology, "Federal Information Processing Standard 46-3, The Data Encryption Standard (DES)," http://csrc.nist.gov/publications/fips/, 1999.
4. A.J. Elbwirt, W. Yip, B. Chetwynd, and C. Paar, "An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists," Proc. Third Advanced Encryption Standard Candidate Conf., pp. 13-27, 2000.
5. K. Gaj and P. Chodowiec, "Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware," Proc. Third Advanced Encryption Standard Candidate Conf., pp. 40-56, 2000.
6. N. Weaver and J. Wawrzynek, "A Comparison of the AES Candidates Amenability to FPGA Implementation," Proc. Third Advanced Encryption Standard Candidate Conf., pp. 28-39, 2000.
7. B. Weeks, M. Bean, T. Rozylowicz, and C. Ficke, "Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms," http://csrc.nist.gov/encryption/aes/round2/NSA-AESfinalreport.pdf, 2000.
8. V. Fischer and M. Drutarovsky, "Two Methods of Rijndael Implementation in Reconfigurable Hardware," Proc. Workshop Cryptographic Hardware and Embedded Systems-CHES 2001, pp. 77-92, 2001.
9. H. Kuo and I. Verbauwhede, "Architectural Optimization for a 1.82Gbits/Sec VLSI Implementation of the AES Rijndael Algorithm," Proc. Workshop Cryptographic Hardware and Embedded Systems-CHES 2001, pp. 51-64, 2001.
10. M. McLoone and J.V. McCanny, "High Performance Single-Chip FPGA Rijndael Algorithm Implementations," Proc. Workshop Cryptographic Hardware and Embedded Systems-CHES 2001, pp. 65-76, 2001.
11. A. Rudra, P.K. Dubey, C.S. Jutla, V. Kumar, J.R. Rao, and P. Rohatgi, "Efficient Rijndael Encryption Implementation with Composite Field Arithmetic," Proc. Workshop Cryptographic Hardware and Embedded Systems-CHES 2001, pp. 171-184, 2001.
12. A. Satoh, S. Morioka, K. Takano, and S. Munetoh, "A Compact Rijndael Hardware Architecture with S-Box Optimization," Proc. Advances in Cryptology-ASIACRYPT 2001, pp. 239-254, 2001.
13. P.C. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Proc. Advances in Cryptology-CRYPTO 1999, pp. 388-397, 1999.
14. K. Tiri, M. Akmal, and I. Verbauwhede, "A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards," Proc. 28th European Solid-State Circuits Conf.-ESSCIRC 2002, 2002.
15. Nat'l Inst. of Standards and Technology, "Special Publication 800-38A 2001 ED, Recommendation for Block Cipher Modes of Operation," http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf 2001.
16. V. Rijmen, "Efficient Implementation of the Rijndael SBox," http://www.esat.kulueven.ac.be/rijmen/rijndael/sbox.pdf, 2000.
17. J. Wolkerstorfer, E. Oswald, and M. Lamberger, "An ASIC implementation of the AES S-Boxes," Topics in Cryptology-CT-RSA 2002, Proc. RSA Conf. 2002, Feb. 2002.
18. J. Wolkerstorfer, "An ASIC Implementation of the AES-MixColumn Operation," Proc. Austrochip 2001, Oct. 2001.