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Volumn 2, Issue , 2002, Pages 1500-1504

A new VLSI implementation of the AES algorithm

Author keywords

Advanced Encryption Standard (AES); ASIC; Cipher; Rijndael; VLSI

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA PRIVACY; OPTIMIZATION; RECONFIGURABLE HARDWARE; STANDARDS; VLSI CIRCUITS;

EID: 84976264700     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCAS.2002.1179063     Document Type: Conference Paper
Times cited : (8)

References (8)
  • 1
    • 84965066515 scopus 로고    scopus 로고
    • ADVANCED ENCRYPTION STANDARD (AES)
    • The National Institute of Standards and Technology (NIST), November 26
    • The National Institute of Standards and Technology (NIST), "ADVANCED ENCRYPTION STANDARD (AES)", Federal Information Processing Standards Publication 197, November 26, 2001
    • (2001) Federal Information Processing Standards Publication 197
  • 3
    • 35248861095 scopus 로고    scopus 로고
    • Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
    • CHES 2001
    • H. Kuo, I. Verbauwhede, "Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm" in CHES 2001, LNCS 2162, pp. 51-64, 2001
    • (2001) LNCS , vol.2162 , pp. 51-64
    • Kuo, H.1    Verbauwhede, I.2
  • 4
    • 0003656468 scopus 로고    scopus 로고
    • Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms
    • Gaithersburg, MD, April 13-14
    • B. Weeks, M. Bean, T. Rozylowicz and C. Ficke, "Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms", in The Third AES Candidate Conference, Gaithersburg, MD, pp. 286-304, April 13-14, 2000.
    • (2000) The Third AES Candidate Conference , pp. 286-304
    • Weeks, B.1    Bean, M.2    Rozylowicz, T.3    Ficke, C.4
  • 5
    • 0005498910 scopus 로고    scopus 로고
    • Hardware Evaluation of the AES Finalists
    • Gaithersburg, MD, April 13-14
    • T. Ichikawa, T. Kasuya, and M. Matsui, "Hardware Evaluation of the AES Finalists" in The Third AES Candidate Conference, Gaithersburg, MD, pp. 279-285, April 13-14, 2000.
    • (2000) The Third AES Candidate Conference , pp. 279-285
    • Ichikawa, T.1    Kasuya, T.2    Matsui, M.3
  • 7
    • 68549125090 scopus 로고    scopus 로고
    • A comparative Study of Performance of AES Final Candidates Using FPGAs
    • CHES 2000
    • Dandalis, Viktor K. Prasanna and Jose D.P. Rolim "A comparative Study of Performance of AES Final Candidates Using FPGAs" in CHES 2000, LNCS 1965, pp. 125-140, 2000
    • (2000) LNCS , vol.1965 , pp. 125-140
    • Dandalis1    Prasanna, V.K.2    Rolim, J.D.P.3
  • 8
    • 84944872607 scopus 로고    scopus 로고
    • Two Methods of Rijndael Implementation in Reconfigurable Hardware
    • CHES 2001
    • Viktor Fischer and Milos Drutarovsky, "Two Methods of Rijndael Implementation in Reconfigurable Hardware" in CHES 2001, LNCS 2162, pp 77-92, 2001
    • (2001) LNCS , vol.2162 , pp. 77-92
    • Fischer, V.1    Drutarovsky, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.