Design and performance testing of a 2.29-GB/s Rijndael processor

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 3, 2003, Pages 569-572

  Verbauwhede, Ingrid ^a   Schaumont, Patrick ^a   Kuo, Henry ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Atmel   (United States)

Author keywords

Advanced encryption standard (AES); Application specific integrated circuit (ASIC); Processor; Rijndael; Secret key cryptography; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; CRYPTOGRAPHY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; VLSI CIRCUITS;

ADVANCED ENCRYPTION STANDARD; RIJNDAEL ENCRYPTION ALGORITHM; SECRET KEY CRYPTOGRAPHY;

MICROPROCESSOR CHIPS;

EID: 0037344419     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.808300     Document Type: Article

References (11)

1. J. Daemen and V. Rijmen, The Design of Rijndael: AES-The Advanced Encryption Standard. New York: Springer-Verlag, 2002.
2. NIST Federal Information Processing Standards (FIBS) PUB 197 Advanced Encryption Standard (2001, Nov.), [Online]. Available: http://www.nist.gov/aes/
3. M. McLoone and J. McCanny, "Single-chip FPGA implementation of the advanced encryption standard algorithm," in Proc. 11th Int. Conf. Field-Programmable Logic and Applications (FPL 2001), LNCS 2147, 2001, pp. 152-161.
4. H. Kuo and I. Verbauwhede, "Architectural optimization for a 1.82 Gb/s VLSI implementation of the AES Rijndael algorithm," in Proc. 3rd Int. Workshop Cryptographic Hardware and Embedded Systems (CHES 2001), LNCS 2162, Paris, France, May 2001, pp. 51-64.
5. J. Wolkerstorfer, E. Oswald, and M. Lamberger, "An ASIC implementation of the AES S-boxes," in Proc. RSA Conf. 2002, San Jose, CA, Feb. 2002, pp. 67-78.
6. U. Mayer, C. Oelsner, and K. Keihler, "Evaluation of different Rijndael implementations for high-end servers," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 2002, pp. 348-351.
7. H. Lipmaa, AES candidates: A survey of implementations. Lab. Theoretical Comput. Sci., Dept. Comput. Sci. Eng., Helsinki Univ. Technol., Helsinki, Finland. [Online]. Available: http://www.tcs.hut.fi/~helger/aes/rijndael.html
8. A. Elbirt, W. Yip, B. Chetwynd, and C. Paar, "An FPGA-based performance evaluation of the AES block cipher candidate algorithms finalists," IEEE Trans. VLSI Syst., vol. 9, pp. 545-557, Aug. 2001.
9. P. Chodowiec, K. Gaj, P. Bellows, and B. Schott, "Experimental testing of the Gigabit IPSec-compliant implementations of Rijndael and triple DES using SLAAC-IV FPGA accelerator board," in Proc. Information Security Conf., LNCS 2200, Malaga, Spain, 2001, p. 220.
10. A. Satoh, S. Morioka, K. Takano, and S. Munetoh, "A compact Rijndael hardware architecture with S-box optimization," in Proc. ASIACRYPT 2001, LNCS 2248, 2001, pp. 239-254.
11. T. Ichikawa, T. Kasuya, and M. Matsui, "Hardware evaluation of the AES finalists," in Proc. 3rd AES Candidate Conf., New York, Apr. 2000, pp. 279-285.