Scalable register file architecture for dynamically scheduled processors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 1996, Pages 179-184

  Wallace, Steven ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MICROCOMPUTERS; PERFORMANCE; PROGRAM PROCESSORS; SCHEDULING; STANDARDS;

DYNAMICALLY SCHEDULED PROCESSORS; HYBRID REGISTER RENAMING TECHNIQUE; MULTIPLE BANKED REGISTER FILE; SCALABLE REGISTER FILE ARCHITECTURE;

SHIFT REGISTERS;

EID: 0029749713     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)