A system-level energy minimization approach using datapath width optimization

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 231-236

  Cao, Y ^a   Yasuura, H ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

Datapath optimization; System level energy minimization; Variable size analysis

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); ENERGY UTILIZATION; MATHEMATICAL MODELS; OPTIMIZATION; PROGRAM PROCESSORS; SIGNAL TO NOISE RATIO; SYSTEMS ANALYSIS;

ENERGY MINIMIZATION;

EMBEDDED SYSTEMS;

EID: 0034863755     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383142     Document Type: Conference Paper

References (12)

1. Embedded system design using soft-core processor and valen-C
2. Language and compiler for optimizing datapath width of embedded systems
3. Soft-core processor architecture for embedded system design
4. A cycle-accurate simulator toolkit for soft-core processors
5. Embedded system cost optimization via data path width adjustment
6. Flexible system lsi for embedded systems and its optimization techniques
7. System-level power estimation and optimization
8. Architectural power analysis: The dual bit type method
9. Power and performance simulator: ESP and its application for 100 MIPS/W Class RISC design
10. Power optimization of variable voltage core-based systems
11. Energy optimization of multilevel cache architectures for RISC and CISC processors
12. A low power hardware/software partitioning approach for core-based embedded systems