Exploiting data-width locality to increase superscalar execution bandwidth

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 395-405

  Loh, Gabriel H ^a  

^a YALE UNIVERSITY   (United States)

Author keywords

Bandwidth; Clocks; Computer science; Delay effects; Microarchitecture; Pipelines; Predictive models; Processor scheduling; Wires

Indexed keywords

BANDWIDTH; CLOCKS; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; PIPELINES; WIRE;

DATA VALUES; DELAY EFFECTS; MICRO ARCHITECTURES; NARROW WIDTH; PREDICTIVE MODELS; PROCESSOR SCHEDULING; SUPERSCALAR PROCESSOR; TEMPORAL LOCALITY;

PIPELINE PROCESSING SYSTEMS;

EID: 69249220832     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176266     Document Type: Conference Paper

References (34)

1. J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 142-151, Los Alamitos, CA, USA, 1993.
2. A. Baniasadi and A. Moshovos. Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors. In Proceedings of the 33rd International Symposium on Microarchitecture, pages 337-347, Monterey, CA, USA, 2000.
3. D. Brooks and M. Martonosi. Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. In Proceedings of the 5th International Symposium on High Performance Computer Architecture, pages 13-22, Orlando, FL, USA, January 1999.
4. D. Brooks and M. Martonosi. Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance. ACM Transactions on Computer Systems, 18(2):89-126, May 2000.
5. D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2. 0. Technical Report 1342, University of Wisconsin, June 1997.
6. G. Z. Chrysos and J. S. Emer. Memory Dependence Prediction Using Store Sets. In Proceedings of the 25th International Symposium on Computer Architecture, pages 142-153, Barcelona, Spain, June 1998.
7. D. Ernst and T. Austin. Efficient Dynamic Scheduling Through Tag Elimination. In Proceedings of the 29th International Symposium on Computer Architecture, pages 37-45, Anchorage, Alaska, May 2002.
8. G. G. et al. A 2. 2 W, 80 Mhz Superscalar RISC Microprocessor. IEEE Journal of Solid-State Circuits, 29(12):1440-1454, December 1994.
9. E. Hao, P.-Y. Chand, and Y. N. Patt. The Effect of Speculatively Updating Branch History on Branch Prediction Accuracy, Revisited. In Proceedings of the 27th International Symposium on Microarchitecture, pages 228-232, San Jose, CA, USA, November 1994.
10. A. Hartstein and T. R. Puzak. The Optimum Pipeline Depth for a Microprocessor. In Proceedings of the 29th International Symposium on Computer Architecture, pages 7-13, Anchorage, Alaska, May 2002.
11. G. Hinton, D. Sager, M. Upton, D. Boggs, D. Karmean, A. Kyler, and P. Roussel. The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal, Q1 2001.
12. M. S. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, S. W. Keckler, and P. Shivakumar. The Optimum Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. In Proceedings of the 29th International Symposium on Computer Architecture, pages 14-24, Anchorage, Alaska, May 2002.
13. R. E. Kessler. The Alpha 21264 Microprocessor. IEEE Micro Magazine, 19(2):24-36, March-April 1999.
14. E. Larson, S. Chatterjee, and T. Austin. MASE: A Novel Infrastructure for Detailed Microarchitectural Modeling. In Proceedings of the 2001 International Symposium on Performance Analysis of Systems and Software, Tucson, AZ, USA, November 2001.
15. C.-C. Lee, I.-C. K. Chen, and T. N. Mudge. The Bi-Mode Branch Predictor. In Proceedings of the 30th International Symposium on Microarchitecture, pages 4-13, Research Triangle Park, NC, USA, December 1997.
16. R. Lee. Accelerating Multimedia with Enhanced Microprocessors. IEEE Micro Magazine, 15(2):22-32, April 1995.
17. M. H. Lipasti and J. P. Shen. Exceeding the Dataflow Limit via Value Prediction. In Proceedings of the 29th International Symposium on Microarchitecture, pages 226-237, Paris, France, December 1996.
18. M. H. Lipasti, C. B. Wilkerson, and J. P. Shen. Value Locality and Load Value Prediction. In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 138-147, Cambridge, MA, USA, October 1996.
19. T. Liu and S.-L. Lu. Performance Improvement with Circuit-Level Speculation. In Proceedings of the 33rd International Symposium on Microarchitecture, Monterey, CA, USA, December 2000.
20. S. McFarling. Combining Branch Predictors. TN 36, Compaq Computer Corporation Western Research Laboratory, June 1993.
21. P. Michaud, A. Seznec, and R. Uhlig. Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. In Proceedings of the 24th International Symposium on Computer Architecture, pages 292-303, Boulder, CO, USA, June 1997.
22. A. Moshovos, S. E. Breach, T. N. Vijaykumar, and G. S. Sohi. Dynamic Speculation and Synchronization of Data Dependences. In Proceedings of the 24th International Symposium on Computer Architecture, pages 181-193, Boulder, CO, USA, June 1997.
23. A. Moshovos and G. S. Sohi. Streamlining Inter-operation Memory Communication via Data Dependence Prediction. In Proceedings of the 30th International Symposium on Microarchitecture, pages 235-245, Research Triangle Park, NC, USA, December 1997.
24. S. Palacharla, N. P. Jouppi, and J. E. Smith. Quantifying the Complexity of Superscalar Processors. CS-TR 1996-1328, University of Wisconsin at Madison, November 1996.
25. S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-Effective Superscalar Processors. In Proceedings of the 24th International Symposium on Computer Architecture, pages 206-218, Boulder, CO, USA, June 1997.
26. S. T. Pan, K. So, and J. T. Rahmeh. Improving the Accuracy of Dynamic Branch Prediction using Branch Correlation. In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 12-15, Boston, MA, USA, October 1992.
27. A. Peleg and U. Weiser. MMX technology extension to the Intel architecture. IEEE Micro Magazine, 16(4):51-59, August 1996.
28. K. Skadron, M. Martonosi, and D. W. Clark. Selecting a Single, Representative Sample for Accurate Simulation of SPECint Benchmarks. TR 595-99, Princeton University Department of Computer Science, January 1999.
29. J. E. Smith. A Study of Branch Prediction Strategies. In Proceedings of the 8th International Symposium on Computer Architecture, pages 135-148, Minneapolis, MN, USA, May 1981.
30. E. Sprangle and D. Carmean. Increasing Processor Performance by Implementing Deeper Pipelines. In Proceedings of the 29th International Symposium on Computer Architecture, pages 25-34, Anchorage, Alaska, May 2002.
31. L. Villa, M. Zhang, and K. Asanovíc. Dynamic Zero Compression for Cache Energy Reduction. In Proceedings of the 33rd International Symposium on Microarchitecture, Monterey, CA, USA, December 2000.
32. T.-Y. Yeh and Y. N. Patt. Two-Level Adaptive Branch Prediction. In Proceedings of the 24th International Symposium on Microarchitecture, pages 51-61, Albuqueque, NM, USA, November 1991.
33. T.-Y. Yeh and Y. N. Patt. Alternative Implementations of Two-Level Adaptive Branch Prediction. In Proceedings of the 19th International Symposium on Computer Architecture, pages 124-134, Gold Coast, Australia, May 1992.
34. T.-Y. Yeh and Y. N. Patt. A Comparison of Dynamic Branch Predictors That Use Two Levels of Branch History. In Proceedings of the 20th International Symposium on Computer Architecture, pages 257-266, 1993.