Carrier quantization at flat bands in MOS devices

IEEE Transactions on Electron Devices

Volumn 46, Issue 2, 1999, Pages 383-387

  Pacelli, Andrea ^a   Spinelli, Alessandro S ^a   Perron, Laura M ^b  

^a POLITECNICO DI MILANO   (Italy)

^b TOWER SEMICONDUCTOR LTD   (Israel)

Author keywords

Capacitance; Modeling; Mos transistor; Quantization

Indexed keywords

CAPACITANCE; CARRIER CONCENTRATION; CHARGE CARRIERS; INTERFACES (COMPUTER); QUANTUM THEORY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SILICA;

CARRIER QUANTIZATION;

MOSFET DEVICES;

EID: 0033080011     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.740906     Document Type: Article

References (13)

1. K. S. Krisch, J. D. Bude, and L. Manchanda, "Gate capacitance attenuation in MOS devices with thin gate dielectrics," IEEE Electron Device Lett., vol. 17, pp. 521-524, Nov. 1996.
2. F. Stern, "Self-consistent results for n-type Si inversion layers," Phys. Rev. B, vol. 5, pp. 4891-4899, 1972.
3. M. J. van Dort, P. H. Woerlee, and A. J. Walker, "A simple model for quantization effects in heavily-doped silicon MOSFET's at inversion conditions," Solid-State Electron., vol. 37, pp. 411-414, 1994.
4. S. Jallepalli, J. Bude, W.-K. Shih, M. R. Pinto, C. M. Maziar, and A. F. Tasch, Jr., "Electron and hole quantization and their impact on deep submicron silicon P- and N-MOSFET characteristics," IEEE Trans. Electron Devices, vol. 44, pp. 297-303, Feb. 1997.
5. J. Suné, P. Olivo, and B. Riccö, "Self-consistent solution of the Poisson and Schrödinger equations in accumulated semiconductorinsulator interfaces," J. Appl. Phys., vol. 70, pp. 337-345, 1991.
6. _, "Quantum-mechanical modeling of accumulation layers in MOS structure," IEEE Trans. Electron Devices, vol. 39, pp. 1732-1739, July 1992.
7. F. Rana, S. Tiwari, and D. A. Buchanan, "Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides," Appl. Phys. Lett., vol. 69, pp. 1104-1106, 1996.
8. J. M. Blacksin, "A Poisson C-V profiler," IEEE Trans. Electron Devices, Vol. ED33, pp. 1387-1389, Sept. 1986.
9. A. Pacelli, "Self-consistent solution of the Schrödinger equation in semiconductor devices by implicit iteration," IEEE Trans. Electron Devices, vol. 44, pp. 1169-1171, July 1997.
10. B. Riccö, R. Versari, and D. Esseni, "Characterization of polysilicongate depletion in MOS structures," IEEE Electron Device Lett., vol. 17, pp. 103-105, Mar. 1996.
11. P. V. Gray and D. M. Brown, "Freeze-out characteristics of the MOS varactor," Appl. Phys. Lett., vol. 13, pp. 247-248, 1968.
12. C.-L. Huang and G. S. Gildenblat, "MOS flat-band capacitance method at low temperatures," IEEE Trans. Electron Devices, vol. 36, pp. 1434-1439, Aug. 1989.
13. N. D. Arora, R. Rios, and C.-L. Huang, "Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance," IEEE Trans. Electron Devices, vol. 42, pp. 935-943, May 1995.