Integrating formal verification into an advanced computer architecture course

IEEE Transactions on Education

Volumn 48, Issue 2, 2005, Pages 216-222

  Velev, Miroslav N ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Abstraction; Boolean satisfiability (SAT); Computer architecture; Formal verification of microprocessors; High level microprocessor design; Logic of Equality with Uninterpreted Functions and Memories (EUFM); Positive Equality; Teaching of formal methods

Indexed keywords

COMPUTER SIMULATION; DIGITAL ARITHMETIC; EDUCATION; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

ABSTRACTION; ARIHTMETIC LOGIC UNIT; HIGH LEVEL MICROPROCESSOR DESIGN; POSITIVE QUALITY;

COMPUTER ARCHITECTURE;

EID: 20344406225     PISSN: 00189359     EISSN: None     Source Type: Journal    
DOI: 10.1109/TE.2004.832880     Document Type: Article

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