Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

Microelectronics Reliability

Volumn 45, Issue 7-8, 2005, Pages 1041-1050

  Mizubayashi, Wataru ^a   Yasuda, Naoki ^a   Okada, Kenji ^a   Ota, Hiroyuki ^a   Hisamatsu, Hirokazu ^a   Iwamoto, Kunihiko ^a   Tominaga, Koji ^a   Yamamoto, Katsuhiko ^a   Horikawa, Tsuyoshi ^a   Nabatame, Toshihide ^a   Satake, Hideki ^a   Toriumi, Akira ^a,b  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRONS; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTOR INSULATOR BOUNDARIES; SILICA;

CARRIER SEPARATION; CONDUCTION MECHANISMS; HOLE CURRENTS; SOFT BREAKDOWN (SBD); STRESS-INDUCED-LEAKAGE-CURRENT (SILC) STATE;

CHARGE CARRIERS;

EID: 20344388523     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.12.016     Document Type: Article

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